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72205LB25TFG PDF预览

72205LB25TFG

更新时间： 2024-11-05 18:56:03
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片内存集成电路
页数 文件大小 规格书
16页 333K
描述
FIFO, 256X18, 15ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, STQFP-64

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中文翻译

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72205LB25TFG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：,针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.23
最长访问时间：15 ns周期时间：25 ns
JESD-30 代码：R-PQFP-G64JESD-609代码：e3
内存密度：4608 bit内存集成电路类型：OTHER FIFO
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：64
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256X18
可输出：YES封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified最大待机电流：0.005 A
子类别：FIFOs最大压摆率：0.06 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

72205LB25TFG 数据手册

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CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18, and 4,096 x 18  
IDT72205LB, IDT72215LB,  
IDT72225LB, IDT72235LB,  
IDT72245LB  
writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering  
needs, such as optical disk controllers, Local Area Networks (LANs), and  
interprocessorcommunication.  
FEATURES:  
• 256 x 18-bit organization array (IDT72205LB)  
• 512 x 18-bit organization array (IDT72215LB)  
• 1,024 x 18-bit organization array (IDT72225LB)  
• 2,048 x 18-bit organization array (IDT72235LB)  
• 4,096 x 18-bit organization array (IDT72245LB)  
• 10 ns read/write cycle time  
TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled  
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread  
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput  
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).  
Thereadclockcanbetiedtothewriteclockforsingleclockoperationorthe  
twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An  
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof  
theoutput.  
ThesynchronousFIFOshavetwofixedflags, Empty (EF)andFull(FF),  
andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The  
offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,  
andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable  
when the FIFO is used in a single device configuration.  
ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The  
XI and XO pins are used to expand the FIFOs. In depth expansion configu-  
ration, First Load (FL) is grounded on the first device and set to HIGH for all  
other devices in the Daisy Chain.  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated  
usinghigh-speedsubmicronCMOStechnology.  
• Empy and Full flags signal FIFO status  
• Easy expandable in depth and width  
• Asynchronous or coincident read and write clocks  
• Programmable Almost-Empty and Almost-Full flags with  
default settings  
• Half-Full flag capability  
• Dual-Port zero fall-through time architecture  
• Output enable puts output data bus in high-impedence state  
• High-performance submicron CMOS technology  
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high  
speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
•
•
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
•
•
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
MARCH 2013  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2766/3  
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