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71V257985BQ PDF预览

71V257985BQ

更新时间: 2024-02-11 15:32:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟动态存储器静态存储器内存集成电路
页数 文件大小 规格书
23页 520K
描述
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165

71V257985BQ 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer包装说明:TBGA, BGA165,11X15,40
Reach Compliance Code:not_compliant风险等级:5.58
最长访问时间:8.5 ns最大时钟频率 (fCLK):87 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:15 mm
内存密度:4718592 bit内存集成电路类型:CACHE DRAM MODULE
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:165
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.03 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.18 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:13 mmBase Number Matches:1

71V257985BQ 数据手册

 浏览型号71V257985BQ的Datasheet PDF文件第2页浏览型号71V257985BQ的Datasheet PDF文件第3页浏览型号71V257985BQ的Datasheet PDF文件第4页浏览型号71V257985BQ的Datasheet PDF文件第5页浏览型号71V257985BQ的Datasheet PDF文件第6页浏览型号71V257985BQ的Datasheet PDF文件第7页 
128K x 36, 256K x 18  
IDT71V2577  
IDT71V2579  
3.3V Synchronous SRAMs  
2.5V I/O, Flow-Through Outputs  
Burst Counter, Single Cycle Deselect  
Description  
Features  
The IDT71V2577/79 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,  
address andcontrolregisters.Therearenoregisters inthedataoutput  
path (flow-through architecture). Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
128K x 36, 256K x 18 memory configurations  
Supports fast access times:  
Commercial:  
– 7.5ns up to 117MHz clock frequency  
CommercialandIndustrial:  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
theendofthewritecycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata  
fora single address presentedtothe SRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBOinputpin.  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA)  
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
0
1
CS , CS  
Chip Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
ZZ  
Asynchronous  
Synchronous  
N/A  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
DD DDQ  
V , V  
Core Power, I/O Power  
Ground  
Supply  
Supply  
SS  
V
N/A  
4877 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V2579.  
OCTOBER 2000  
1
©2000ntegratedDeviceTechnology,Inc.  
DSC-4877/06  

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