Datasheet > 71V416S10PH

71V416S10PH

更新时间： 2023-02-26 13:32:45

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器光电二极管
页数	文件大小	规格书
9页	1397K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

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71V416S10PH 数据手册

IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

Pin Configurations - SOJ/TSOP

Pin Configurations - 48 BGA

A17

A16

A15

BLE

I/O

I/O8

BHE

BLE

I/O

I/O10

I/O11

I/O12

I/O13

I/O9

I/O 0

I/O 1

I/O 2

I/O 3

I/O 15

I/O 14

I/O 13

I/O 12

VSS

I/O

A17

VDD

I/O

A16

VSS

SO44-1

SO44-2

I/O

A14

A15

I/O14

I/O15

I/O 4

I/O 5

I/O 6

I/O 7

I/O 11

I/O 10

I/O 9

I/O

A12

A13

I/O 8

NC*

A10

A11

A14

A13

A12

3624 tbl 11

A11

A10

3624 drw 02

*Pin 28 can either be a NC or connected to Vss

Top View

SOJCapacitance

(TA = +25°C, f = 1.0MHz)

PinDescriptions

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

- A17

Address Inputs

Input

Chip Select

Input

I/O

CIN

Write Enable

CI/O

3624 tbl 02

Output Enable

High Byte Enable

Low Byte Enable

Data Input/Output

3.3V Power

BHE

BLE

48BGACapacitance

(TA = +25°C, f = 1.0MHz)

I/O0 - I/O15

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

VDD

Pwr

CIN

VSS

Ground

Gnd

CI/O

3624 tbl 01

3624 tbl 02b

NOTE:

1. This parameter is guaranteed by device characterization, but not production

tested.

6.422

123 4 5 6 7...9

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