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7140SA20TFG PDF预览

7140SA20TFG

更新时间: 2024-01-20 14:56:01
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 272K
描述
Dual-Port SRAM, 1KX8, 20ns, CMOS, PQFP64

7140SA20TFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:QFP, QFP64,.47SQ,20
Reach Compliance Code:compliant风险等级:5.25
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
内存密度:8192 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:2
端子数量:64字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.015 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.25 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

7140SA20TFG 数据手册

 浏览型号7140SA20TFG的Datasheet PDF文件第2页浏览型号7140SA20TFG的Datasheet PDF文件第3页浏览型号7140SA20TFG的Datasheet PDF文件第4页浏览型号7140SA20TFG的Datasheet PDF文件第5页浏览型号7140SA20TFG的Datasheet PDF文件第6页浏览型号7140SA20TFG的Datasheet PDF文件第7页 
IDT7130SA/LA  
IDT7140SA/LA  
HIGH SPEED  
1K X 8 DUAL-PORT  
STATIC SRAM  
Features  
On-chip port arbitration logic (IDT7130 Only)  
High-speed access  
BUSY output flag on IDT7130; BUSY input on IDT7140  
INT flag for port-to-port communication  
– Commercial: 20/25/35/55/100ns (max.)  
– Industrial: 25/55/100ns (max.)  
– Military: 25/35/55/100ns (max.)  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin  
PLCC, and 64-pin STQFP and TQFP  
Green parts available, see ordering information  
Low-power operation  
– IDT7130/IDT7140SA  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
– IDT7130/IDT7140LA  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
MASTER IDT7130 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT7140  
Functional Block Diagram  
OER  
OEL  
CE  
R/W  
L
CE  
R/W  
R
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSY  
L
BUSYR  
A
9L  
0L  
A
9R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
10  
10  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
R
OE  
R
R/W  
L
(2)  
(2)  
INT  
R
INTL  
2689 drw 01  
NOTES:  
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.  
IDT7140 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor.  
JANUARY 2013  
1
DSC-2689/15  
©2013 IntegratedDeviceTechnology,Inc.  

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