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71342LA20PFG PDF预览

71342LA20PFG

更新时间: 2024-02-27 23:34:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
14页 318K
描述
HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM

71342LA20PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LQFP, QFP64,.66SQ,32针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.38
Samacsys Description:TQFP 14.0 X 14.0 X 1.4 MM最长访问时间:20 ns
其他特性:SEMAPHORE; AUTOMATIC POWER-DOWN; BATTERY BACKUPI/O 类型:COMMON
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:14 mm内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:2端子数量:64
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.24 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

71342LA20PFG 数据手册

 浏览型号71342LA20PFG的Datasheet PDF文件第6页浏览型号71342LA20PFG的Datasheet PDF文件第7页浏览型号71342LA20PFG的Datasheet PDF文件第8页浏览型号71342LA20PFG的Datasheet PDF文件第10页浏览型号71342LA20PFG的Datasheet PDF文件第11页浏览型号71342LA20PFG的Datasheet PDF文件第12页 
IDT71342SA/LA  
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore  
Industrial and Commercial Temperature Ranges  
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)  
tWC  
ADDRESS  
OE  
(6)  
tAS  
(3)  
tAW  
tWR  
CE or SEM(9)  
(7)  
(2)  
tHZ  
tWP  
R/W  
(7)  
(7)  
tWZ  
tHZ  
t
LZ  
tOW  
(4)  
(4)  
DATAOUT  
DATAIN  
tDH  
tDW  
2721 drw 10  
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)  
t
WC  
ADDRESS  
tAW  
CE or SEM(9)  
(2)  
(6)  
AS  
(3)  
t
tEW  
t
WR  
R/W  
t
DW  
t
DH  
DATAIN  
2721 drw 11  
NOTES:  
1. R/W or CE must be HIGH during all address transitions.  
2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.  
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.  
4. During this period, the I/O pins are in the output state, and input signals must not be applied.  
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.  
6. Timing depends on which enable signal (CE or R/W) is asserted last.  
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load  
(Figure 2).  
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus  
for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.  
9. To access SRAM, CE =VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.  
9
6.42  

71342LA20PFG 替代型号

型号 品牌 替代类型 描述 数据表
71342LA20PFG IDT

当前型号

HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM
71342LA20PFG8 IDT

完全替代

HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM
71342LA20JG8 IDT

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