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7133SA90GG8 PDF预览

7133SA90GG8

更新时间: 2024-02-25 00:57:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 311K
描述
Dual-Port SRAM, 2KX16, 90ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68

7133SA90GG8 技术参数

生命周期:Active包装说明:PGA,
Reach Compliance Code:compliant风险等级:5.58
Is Samacsys:N最长访问时间:90 ns
JESD-30 代码:S-CPGA-P68内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端子数量:68
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX16
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:PIN/PEG
端子位置:PERPENDICULARBase Number Matches:1

7133SA90GG8 数据手册

 浏览型号7133SA90GG8的Datasheet PDF文件第5页浏览型号7133SA90GG8的Datasheet PDF文件第6页浏览型号7133SA90GG8的Datasheet PDF文件第7页浏览型号7133SA90GG8的Datasheet PDF文件第9页浏览型号7133SA90GG8的Datasheet PDF文件第10页浏览型号7133SA90GG8的Datasheet PDF文件第11页 
IDT7133SA/LA,IDT7143SA/LA  
High-Speed 2K x 16 Dual-Port RAM  
Military, Industrial and Commercial Temperature Ranges  
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)  
tRC  
ADDRESS  
t
AA  
tOH  
tOH  
DATAOUT  
PREVIOUS DATA VALID  
DATA VALID  
BUSYOUT  
(3,4)  
2746 drw 07  
tBDD  
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)  
(4)  
tACE  
CE  
OE  
(4)  
(2)  
tAOE  
tHZ  
(1)  
(2)  
tLZ  
tHZ  
DATAOUT  
VALID DATA  
(1)  
tLZ  
tPU  
tPD  
ICC  
CURRENT  
50%  
50%  
ISB  
2746 drw 08  
NOTES:  
1. Timing depends on which signal is asserted last, OE or CE.  
2. Timing depends on which signal is deasserted first, OE or CE.  
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no  
relationship to valid output data.  
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.  
5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.  
6.42  
8

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