Datasheet > 7133LA90F

7133LA90F

更新时间： 2024-01-03 16:01:57

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 90ns, CMOS, CQFP68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, FP-68

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7133LA90F 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFF, QFL68,.95SQ	针数：	68
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.19
最长访问时间：	90 ns	I/O 类型：	COMMON
JESD-30 代码：	S-CQFP-F68	JESD-609代码：	e0
长度：	24.0792 mm	内存密度：	32768 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	16
功能数量：	1	端口数量：	2
端子数量：	68	字数：	2048 words
字数代码：	2000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2KX16	输出特性：	3-STATE
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QFF
封装等效代码：	QFL68,.95SQ	封装形状：	SQUARE
封装形式：	FLATPACK	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	3.683 mm
最大待机电流：	0.0015 A	最小待机电流：	2 V
子类别：	SRAMs	最大压摆率：	0.25 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	24.0792 mm
Base Number Matches：	1

7133LA90F 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Functional Description

The IDT7133/43 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT7133/43 has an automatic power down

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted. Non-contention READ/WRITE conditions

are illustrated in Truth Table 1.

LEFT

RIGHT

R/W

IDT7133

MASTER

BUSY

270Ω

VCC

R/W

IDT7143

SLAVE

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAMhaveaccessedthesamelocationatthesametime. Italsoallows

one of the two accesses to proceed and signals the other side that the

RAMis “busy”. The BUSY pincanthenbe usedtostallthe access until

the operation on the other side is completed. If a write operation has

been attempted from the side that receives a BUSY indication, the

write signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applica-

2746 drw 15

BUSY

Figure 4. Busy and chip enable routing for both width and depth expansion

with the IDT7133 (MASTER) and the IDT7143 (SLAVE).

Expanding the data bus width to 32 bits or more in a Dual-Port RAM

tions. Insome cases itmaybe usefultologicallyORthe BUSY outputs systemimpliesthatseveralchipswillbeactiveatthesametime.Ifeach

togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe chip includes a hardware arbitrator, and the addresses for each chip

event of an illegal or illogical operation. If the write inhibit function of arrive at the same time, it is possible that one will activate its BUSY^L

BUSY logic is not desirable, the BUSY logic can be disabled by using while another activates its BUSYR signal. Both sides are now BUSY

the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely and the CPUs will await indefinitely for their port to become free.

as a write inhibit input pin. Normal operation can be programmed by

To avoid the “Busy Lock-Out” problem, IDT has developed a

tyingtheBUSY pins HIGH. Ifdesired, unintendedwrite operations can MASTER/SLAVEapproachwhereonlyonehardwarearbitrator,inthe

be prevented to a port by tying the BUSY pin for that port LOW. The MASTER, is used. The SLAVE has BUSY inputs which allow an

BUSY outputs on the IDT 7133 RAM are open drain and require pull- interface to the MASTER with no external components and with a

up resistors.

speed advantage over other systems.

WhenexpandingDual-PortRAMs inwidth,thewritingoftheSLAVE

RAMs must be delayed until after the BUSY input has settled.

Otherwise,theSLAVEchipmaybeginawritecycleduringacontention

situation. Conversely, the write pulse must extend a hold time past

BUSY to ensure that a write cycle takes place after the contention is

resolved.ThistimingisinherentinallDual-Portmemorysystemswhere

morethanonechipisactiveatthesametime.

The write pulse to the SLAVE should be delayed by the maximum

arbitration time of the MASTER. If, then, a contention occurs, the write

totheSLAVEwillbeinhibitedduetoBUSYfromtheMASTER.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT7133/43 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master, use the BUSY signal as a write inhibit signal. Thus on the

IDT7133RAMtheBUSYpinisanoutputandontheIDT7143RAM,the

BUSY pin is an input (see Figure 3).

6.42

1...11 12 131415 16

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与7133LA90F相关器件

型号	品牌	描述	获取价格	数据表
7133LA90FB	IDT	Dual-Port SRAM, 2KX16, 90ns, CMOS, CQFP68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, FP-68	获取价格
7133LA90FG	IDT	Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP68, 1.180 X 1.180 INCH, 0.160 INCH, GREEN, FP-68	获取价格
7133LA90FG8	IDT	Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP68, 1.180 X 1.180 INCH, 0.160 INCH, GREEN, FP-68	获取价格
7133LA90FGB	IDT	Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP68, 1.180 X 1.180 INCH, 0.160 INCH, GREEN, FP-68	获取价格
7133LA90J8	IDT	PLCC-68, Reel	获取价格
7133LA90PF	IDT	Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	获取价格

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