Datasheet > 存储 > SRAM> 7133SA25J8

7133SA25J8

更新时间： 2024-12-02 08:46:39

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
17页	311K
描述
PLCC-68, Reel

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中文翻译

获取价格

数据手册

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7133SA25J8 数据手册

IDT7133SA/LA

IDT7143SA/LA

HIGH SPEED

2K X 16 DUAL-PORT

SRAM

Features

◆

High-speed access

MASTER IDT7133 easily expands data bus width to 32 bits

or more using SLAVE IDT7143

–

Military:35/55/70/90ns(max.)

Industrial:25/55ns(max.)

Commercial:20/25/35/45/55/70/90ns(max.)

◆

On-chip port arbitration logic (IDT7133 only)

BUSY output flag on IDT7133; BUSY input on IDT7143

Fully asynchronous operation from either port

Battery backup operation–2V data retention

TTL-compatible; single 5V (±10%) power supply

Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-

pin TQFP

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Low-power operation

–

IDT7133/43SA

Active:1150mW(typ.)

Standby: 5mW (typ.)

IDT7133/43LA

–

◆

Active:1050mW(typ.)

Standby: 1mW (typ.)

◆

Versatile control for write: separate write control for lower

and upper byte of each port

◆

Green parts available, see ordering information

Functional Block Diagram

R/WRUB

R/WLUB

CER

R/WLLB

R/WRLB

I/O8L - I/O15L

I/O0L - I/O7L

(1)

I/O8R - I/O15R

I/O

CONTROL

I/O

CONTROL

I/O0R - I/O7R

(1)

BUSY

10R

10L

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

ARBITRATION

LOGIC

(IDT7133 ONLY)

2746 drw 01

NOTE:

1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.

IDT7143 (SLAVE): BUSY is input.

JANUARY 2012

DSC 2746/14

12 3 4 5 6 7...17

中文翻译

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