Datasheet > 7133LA45JB

7133LA45JB

更新时间： 2024-02-07 00:36:52

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

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7133LA45JB 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I – Non-Contention Read/Write Control⁽⁴⁾

(1)

LEFT OR RIGHT PORT

R/WLB

R/WUB

I/O0-7

I/O8-15

Function

Port Disabled and in Power Down Mode, ISB2, ISB4

CER = CEL = VIH, Power Down Mode, ISB1 or ISB3

DATAIN

DATA^IN

DATAIN

DATAOUT

Data on Lower Byte and Upper Byte Written into Memory ⁽²⁾

Data on Lower Byte Written into Memory⁽²⁾, Data in Memory Output on

Upper Byte⁽³⁾

Data in Memory Output on Lower Byte⁽³⁾, Data on Upper Byte Written into

Memory⁽²⁾

DATAOUT

DATAIN

Data on Lower Byte Written into Memory⁽²⁾

DATAOUT

DATAIN

DATAOUT

Data on Upper Byte Written into Memory ⁽²⁾

Data in Memory Output on Lower Byte and Upper Byte

High Impedance Outputs

2746 tbl 13

NOTES:

1. A0L - A10L≠A0R - A10R

2. If BUSY = LOW, data is not written.

3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing.

4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte

Truth Table II — Address BUSY

Arbitration

Inputs

Outputs

0L-A10L

(1)

0R-A10R

Function

Normal

BUSY

BUSYR

NO MATCH

MATCH

(2)

Write Inhibit⁽³⁾

2746 tbl 14

NOTES:

1. Pins BUSY^Land BUSYR are both outputs on the IDT7133 (MASTER). Both are

inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits

writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable

inputs of this port. “H” if the inputs to the opposite port became stable after the

address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR

= VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSY^Routputs are driving LOW regardless of actual logic level on

the pin.

6.42

1...12 13 141516

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