Datasheet > 7133LA45JB

7133LA45JB

更新时间： 2023-02-26 14:14:06

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

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7133LA45JB 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)^(1,5,8)

tWC

ADDRESS

(6)

tAS

(3)

tWR

tAW

(7)

(2)

tHZ

tWP

R/W⁽⁹⁾

(7)

tHZ

tLZ

tOW

(4)

DATAOUT

DATAIN

tDW

2746 drw 09

Write Cycle No. 2 (CE Controlled Timing)^(1,5)

tWC

ADDRESS

tAW

(6)

(2)

tAS

tWR

R/W⁽⁹⁾

tDW

tDH

DATAIN

2746 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. Timing depends on which enable signal is de-asserted first, CE or OE.

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. R/W for either upper or lower byte.

6.42

1...8 9 101112 13 14...16

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