Datasheet > 7133LA45JB

7133LA45JB

更新时间： 2024-02-11 12:02:36

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

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7133LA45JB 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY^(1,2,3)

MATCH

ADDR"A"

R/W"A"

tWP

tDW

tDH

VALID

DATAIN"A"

(1)

APS

MATCH

ADDR"B"

tBDA

tBDD

BUSY"B"

tWDD

DATAOUT "B"

VALID

(4)

DDD

2746 drw 11

NOTES:

1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY⁽³⁾

tWP

R/W"A"

tWB

BUSY"B"

(1)

tWH

R/W"B"

(2)

2746 drw 12

NOTES:

1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).

2. BUSY is asserted on port "B" blocking R/W^"B", until BUSY"B" goes HIGH.

3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.42

1...9 10 111213 14 15 16

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