IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range ( VDD= 3.3V ± 0.3V)
70V9169/59L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
Unit
µA
µA
V
___
___
___
|
V
DD = 3.6V, VIN = 0V t
CE = VIH or CE = VIL, VOUT = 0V t
OL = +4mA
OH = -4mA
o
V
DD
5
5
|
1
o VDD
V
V
OL
OH
I
0.4
___
Output High Voltage
I
2.4
V
5655 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9169/59L6
Com'l Only
70V9169/59L7
Com'l & Ind
70V9169/59L9
Com'l Only
Symbol
Parameter
Test Condition
and CE = VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
280
330
70
Typ.(4)
Max.
Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
L
L
L
L
L
L
175
330
155
155
40
135
230
CE
L
R
,
Outputs Disabled,
f = fMAX
(1)
____
____
____
____
IND
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
50
80
30
60
CE
L = CER = VIH
(1)
____
____
____
____
40
80
f = fMAX
ISB2
Standby
CE"A" = VIL and
COM'L
IND
115
185
105
170
95
155
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
____
____
____
105
0.5
0.5
95
180
3.0
3.0
160
(1)
ISB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL
CE >VDD - 0.2V,
and
mA
mA
COM'L
IND
L
L
0.5
3.0
0.5
3.0
R
V
V
IN > VDD- 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
ISB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
COM'L
IND
L
L
105
175
85
145
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
V
IN > VDD- 0.2V or
IN < 0.2V, Active Port,
____
____
____
____
95
175
V
Outputs Disabled, f = fMAX
(1)
5655 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD =3.3V,TA =25°C forTyp,andarenotproductiontested.ICC DC(f=0)=90mA(Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.462