Datasheet > 70V9159L7PFGI

70V9159L7PFGI

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L7PFGI 数据手册

IDT70V9169/59L

HIGH-SPEED 3.3V 16/8K X 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

◆

Features:

Full synchronous operation on both ports

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:6.5/7.5/9ns(max.)

– Industrial: 7.5ns (max.)

– 3.5ns setup to clock and 0ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

LVTTL- compatible, single 3.3V ( 0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for 83 MHz

◆

Low-power operation

– IDT70V916/59L/59L

◆

Active:450mW(typ.)

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

◆

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin fine pitch Ball Grid Array (fpBGA) packages.

Functional Block Diagram

R/WR

R/W

OEL

OER

CE0R

CE1R

CE0L

CE1L

0/1

FT/PIPE

0/1

FT/PIPE

I/O0R - I/O8R

I/O0L - I/O8L

I/O

Control

I/O

Control

(1)

A13L

A13R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

CNTRST

ADS

CNTEN

CNTRST

5655 drw 01

NOTE:

1. A13 is a NC for IDT70V9159.

FEBRUARY 2018

DSC-5655/5

12 3 4 5 6 7...16

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