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70V914S12PF PDF预览

70V914S12PF

更新时间: 2023-03-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
10页 108K
描述
TQFP-80, Tray

70V914S12PF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14MM, 1.40 MM HEIGHT, TQFP-80针数:80
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:N最长访问时间:25 ns
JESD-30 代码:S-PQFP-G80JESD-609代码:e3
长度:14 mm内存密度:36864 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:80字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX9封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

70V914S12PF 数据手册

 浏览型号70V914S12PF的Datasheet PDF文件第4页浏览型号70V914S12PF的Datasheet PDF文件第5页浏览型号70V914S12PF的Datasheet PDF文件第6页浏览型号70V914S12PF的Datasheet PDF文件第7页浏览型号70V914S12PF的Datasheet PDF文件第9页浏览型号70V914S12PF的Datasheet PDF文件第10页 
IDT70V914S  
High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.)  
tCYC  
tCYC  
tCH  
tCL  
tCH  
tCL  
CLK  
CLKEN  
CE  
tS  
tH  
(1)  
R/W  
An + 1(1)  
ADDRESS  
DATAIN  
An  
An + 1  
An + 2  
Dn + 2  
(1)  
Dn + 1  
(3)  
tCD  
tCKHZ  
DATAOUT  
Qn  
(3)  
tCKLZ  
5616 drw 08  
Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.)  
(4)  
tCYC  
tCH  
tCL  
CLK  
CLKEN  
CE  
tS  
tH  
R/W  
ADDRESS  
DATAIN  
An  
An + 1  
Dn + 1  
tCD  
DATAOUT  
Qn  
(3)  
t
CKLZ  
tOHZ  
OE  
5616 drw 09  
NOTES:  
1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must  
be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle.  
2. OE LOW throughout.  
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to  
be repeated.  
6.42  
8

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