IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
interface. Registered inputs provide minimal setup and hold times on
address,dataandallcriticalcontrolinputs.
FunctionalDescription
The IDT70V7599 is a high-speed 128Kx36 (4 Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
2Kx36banks.BasedonastandardSRAMcoreinsteadofatraditionaltrue
dual-portmemorycore,thisbank-switchabledeviceoffersthebenefitsof
increased density and lower cost-per-bit while retaining many of the
featuresoftruedual-ports.Thesefeaturesincludesimultaneous,random
accesstothesharedarray,separateclocksperport,166MHzoperating
speed,full-boundarycounters,andpinoutscompatiblewiththeIDT70V3599
(128Kx36)dual-portfamily.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
theinternalcircuitryoneachport(individuallycontrolled)toreducestatic
powerconsumption.Dualchipenablesalloweasierbankingofmultiple
IDT70V7599S for depth expansion configurations. Two cycles are
requiredwithCE0LOWandCE1HIGHtoreadvaliddataontheoutputs.
Thetwoportsarepermittedindependent,simultaneousaccessinto
separatebankswithinthesharedarray.Accessbytheportsintospecific
banks are controlled by the bank address pins under the user's direct
Depth and Width Expansion
The IDT70V7599 features dual chip enables (refer to Truth
control:eachportcanaccessanybankofmemorywiththesharedarray Table I) in order to facilitate rapid and simple depth expansion with no
thatisnotcurrentlybeingaccessedbytheoppositeport(i.e.,BA0L -BA5L requirements for external logic. Figure 4 illustrates how to control the
≠BA0R-BA5R).Intheeventthatbothportstrytoaccessthesamebank various chip enables in order to expand two devices in depth.
atthesametime,neitheraccesswillbevalid,anddataatthetwospecific
TheIDT70V7599canalsobeusedinapplicationsrequiringexpanded
addressestargetedbytheportswithinthatbankmaybecorrupted(inthe width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the
casethateitherorbothportsarewriting)ormayresultininvalidoutput(in devices can be grouped as necessary to accommodate applications
the case thatbothports are tryingtoread).
needing 72-bits or wider.
TheIDT70V7599providesatruesynchronousDual-PortStaticRAM
(1)
BA6
IDT70V7599
IDT70V7599
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V7599
IDT70V7599
CE1
CE1
CE0
CE0
BE,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
ADS,
REPEAT,
CNTEN
5626 drw 20
Figure 4. Depth and Width Expansion with IDT70V7599
NOTE:
1.
In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are
controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently
being accessed by the opposite port (i.e., BA0L - BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither
access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are
writing) or may result in invalid output (in the case that both ports are trying to read).
6.42
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