Datasheet > 70V7599S200BFG

70V7599S200BFG

更新时间： 2022-12-29 21:43:09

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	755K
描述
HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

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70V7599S200BFG 数据手册

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

Chip Enables

CE0L

CE1L

CE0R, CE1R

R/W

BA0L - BA5L

0L - A10L

I/O0L - I/O35L

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0L - BE3L

R/W

BA0R - BA5R

0R - A10R

I/O0R - I/O35R

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0R - BE3R

Read/Write Enable

Output Enable

Bank Address⁽⁴⁾

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat⁽³⁾

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)⁽¹⁾

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

DDQL

DDQR

(1,2)

OPT

OPTR

Option for selecting VDDQX

Power (3.3V)⁽¹⁾

Ground (0V)

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

TDI

TDO

TCK

Test Data Input

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

TMS

TRST

5626 tbl 01

6.42

1 2 3 456 7 8...22

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