IDT70V659/58/57S
HIGH-SPEED 3.3V
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
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True Dual-Port memory cells which allow simultaneous
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
access of the same memory location
High-speed access
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– Commercial:10/12/15ns(max.)
– Industrial:12/15ns(max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
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On-chip port arbitration logic
Green parts available, see ordering information
Functional Block Diagram
BE3L
BE3R
BE2R
BE2L
BE1L
BE0L
BE1R
BE0R
R/WL
R/
WR
B B B B B B B B
E E E E E E E E
0
L
1
L
2
L
3
L
3
2 1
0
CE0L
CE1L
CE0R
CE1R
R R R R
OEL
OER
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout18-26_L
Dout27-35_L
128/64/32K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Di n_L
Di n_R
I/O0R -I/O35R
(1)
(1)
16 L
A
16R
Address
Decoder
A
Address
Decoder
ADDR_L
ADDR_R
A0R
A0L
CE0L
CE1L
ARBITRATION
CE0R
CE1R
INTERRUPT
SEMAPHORE
LOGIC
OE
L
OE
R
R/W
L
R/W
R
(2,3)
L
(2,3)
R
BUSY
SEM
INT
BUSY
SEM
M/S
L
L
R
(3)
(3)
INT
R
TMS
TCK
TDI
JTAG
TDO
TRST
NOTES:
4869 drw 01
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2018
1
©2018 Integrated Device Technology, Inc.
DSC-4869/8