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70V3579S6BFG PDF预览

70V3579S6BFG

更新时间: 2024-02-09 20:45:10
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器输出元件内存集成电路
页数 文件大小 规格书
17页 208K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

70V3579S6BFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA, BGA208,17X17,32针数:208
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.21
最长访问时间:6 ns其他特性:PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
最大时钟频率 (fCLK):83 MHzI/O 类型:COMMON
JESD-30 代码:S-PBGA-B208JESD-609代码:e1
长度:15 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端口数量:2端子数量:208
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA208,17X17,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.7 mm最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.31 mA
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:15 mm
Base Number Matches:1

70V3579S6BFG 数据手册

 浏览型号70V3579S6BFG的Datasheet PDF文件第2页浏览型号70V3579S6BFG的Datasheet PDF文件第3页浏览型号70V3579S6BFG的Datasheet PDF文件第4页浏览型号70V3579S6BFG的Datasheet PDF文件第5页浏览型号70V3579S6BFG的Datasheet PDF文件第6页浏览型号70V3579S6BFG的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 32K x 36  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
IDT70V3579S  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features:  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, single 3.3V ( 150mV) power supply for  
core  
LVTTL compatible, selectable 3.3V ( 150mV)/2.5V ( 125mV)  
power supply for I/Os and control signals on each port  
Industrial temperature range (-40°C to +85°C) is  
available for selected speeds  
– Commercial:4.2/5/6ns(max.)  
– Industrial: 5ns (max)  
Pipelined output mode  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)  
– Fast 4.2ns clock to data out  
Available in a 208-pin Plastic Quad Flatpack (PQFP) and  
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid  
Array  
– 1.8ns setup to clock and 0.7ns hold on all control, data, and  
address inputs @ 133MHz  
Green parts available, see ordering information  
Functional Block Diagram  
BE3L  
BE3R  
BE2R  
BE1R  
BE0R  
BE2L  
BE1L  
BE0L  
R/W  
L
R/WR  
B
B
B
B
B
B B B  
W W W W W WW W  
0
L
1
L
2
L
3
L
3
R
2
1
0
R
CE0L  
R R  
CE0R  
CE1L  
CE1R  
OE  
L
OER  
Dout0-8_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
32K x 36  
MEMORY  
ARRAY  
I/O0L- I/O35L  
Din_L  
I/O0R - I/O35R  
Din_R  
,
CLK  
L
CLKR  
A
14L  
A
A
14R  
0R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
ADDR_L  
ADDR_R  
CNTRST  
ADS  
CNTEN  
L
CNTRST  
ADS  
CNTEN  
R
R
L
L
R
4830 tbl 01  
FEBRUARY 2018  
1
DSC 4830/18  
©2018 Integrated Device Technology, Inc.  

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