Datasheet > 70V3589

70V3589

更新时间： 2024-09-24 14:57:11

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
24页	339K
描述
64K x 36 Sync, 3.3V Dual-Port RAM, Pipelined/Flow-Through, Interleaved I/O's

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中文翻译

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数据手册

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70V3589 数据手册

HIGH-SPEED 3.3V 128/64K x 36

70V3599/89S

SYNCHRONOUS DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

High-speed data access

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

GridArray(BGA)

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

◆

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

◆

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

BE3R

BE3L

BE2L

BE1L

BE0L

BE2R

BE1R

BE0R

FT/PIPE

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

CE1R

CE1L

B B B

B B B B

1/0

W W W W W W W W

Dout0-8_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

1d 0d 1c 0c

1b 0b 1a 0a

0a 1a 0b 1b

0c 1c 0d 1d

d c b a

0/1

FT/PIPE

ab cd

128K x 36

MEMORY

ARRAY

I/O0L - I/O35L

I/O0R - I/O35R

Din_L

Din_R

CLKR

CLKL

(1)

16L

16R

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

5617 tbl 01

TDI

TCK

TMS

TRST

NOTE:

JTAG

TDO

1. A16 is a NC for IDT70V3589.

Feb.03.20

12 3 4 5 6 7...24

中文翻译

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与70V3589相关器件

型号	品牌	获取价格	描述	数据表
70V3589S133BCG	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BCG8	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BCGI	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BCGI8	IDT	获取价格	Multi-Port SRAM, 64KX36, 4.2ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GRE
70V3589S133BFG	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BFG8	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BFGI	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133BFGI8	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70V3589S133DR8	IDT	获取价格	Application Specific SRAM, 64KX36, 4.2ns, CMOS, PQFP208
70V3589S133DRG	IDT	获取价格	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM

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