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70V08L25PFG8 PDF预览

70V08L25PFG8

更新时间: 2024-11-24 15:45:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 662K
描述
Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100

70V08L25PFG8 技术参数

生命周期:Active包装说明:QFP,
Reach Compliance Code:compliantHTS代码:8542.32.00.41
风险等级:5.74最长访问时间:25 ns
JESD-30 代码:S-PQFP-G100内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX8
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子位置:QUADBase Number Matches:1

70V08L25PFG8 数据手册

 浏览型号70V08L25PFG8的Datasheet PDF文件第2页浏览型号70V08L25PFG8的Datasheet PDF文件第3页浏览型号70V08L25PFG8的Datasheet PDF文件第4页浏览型号70V08L25PFG8的Datasheet PDF文件第5页浏览型号70V08L25PFG8的Datasheet PDF文件第6页浏览型号70V08L25PFG8的Datasheet PDF文件第7页 
IDT70V08S/L  
HIGH-SPEED 3.3V  
64K x 8 DUAL-PORT  
STATIC RAM  
Features  
IDT70V08 easily expands data bus width to 16 bits or  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
– Commercial:15/20/25/35ns(max.)  
– Industrial: 20ns (max.)  
Busy and Interrupt Flags  
Low-power operation  
On-chip port arbitration logic  
– IDT70V08S  
Full on-chip hardware support of semaphore signaling  
between ports  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP  
– IDT70V08L  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Dual chip enables allow for depth expansion without  
external logic  
Green parts available, see ordering information  
Functional Block Diagram  
R/WL  
CE0L  
CE1L  
R/WR  
CE0  
R
CE1R  
OEL  
OER  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
0-7R  
I/O  
(1,2)  
(1,2)  
R
BUSY  
L
BUSY  
64Kx8  
MEMORY  
ARRAY  
70V08  
A
15L  
A
A
15R  
0R  
Address  
Decoder  
Address  
Decoder  
A
0L  
A15L  
A15R  
A0L  
CE 0L  
CE1L  
A0R  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE1R  
OER  
OEL  
R/WL  
R/WR  
SEM  
INT  
L
L
SEM  
R
(2)  
(2)  
INT  
R
M/S(1)  
3740 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
FEBRUARY 2015  
1
DSC-3740/9  
©2015 Integrated Device Technology, Inc.  

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