Datasheet > 70V05S55PF8

70V05S55PF8

更新时间： 2025-09-22 19:18:03

品牌	Logo	应用领域
瑞萨 - RENESAS		存储
页数	文件大小	规格书
24页	478K
描述
存储容量(Mb):64Kb（8K x 8）;内存数据长度(bit):8K ;字编码数(k):8K ;元器件封装:64-TQFP（14x14）;

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中文翻译

获取价格

数据手册

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70V05S55PF8 数据手册

70V05S/L

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PLCC and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆

–

Commercial: 15ns (max.)

Industrial: 20ns (max.)

◆

Low-power operation

◆

–

IDT70V05L

Active:380mW(typ.)

Standby: 660μW (typ.)

◆

IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆

Green parts available, see ordering information

Functional Block Diagram

OEL

OER

CEL

CER

R/W

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSY

12L

12R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INTL

SEM

M/S

(2)

INTR

2942 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

JUNE 2019

DSC 2941/12

12 3 4 5 6 7...24

中文翻译

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