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709389L9PF9 PDF预览

709389L9PF9

更新时间: 2024-10-29 07:04:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 171K
描述
TQFP-100, Tray

709389L9PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LFQFP,针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:20 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

709389L9PF9 数据手册

 浏览型号709389L9PF9的Datasheet PDF文件第2页浏览型号709389L9PF9的Datasheet PDF文件第3页浏览型号709389L9PF9的Datasheet PDF文件第4页浏览型号709389L9PF9的Datasheet PDF文件第5页浏览型号709389L9PF9的Datasheet PDF文件第6页浏览型号709389L9PF9的Datasheet PDF文件第7页 
HIGH-SPEED 64K x 18  
IDT709389L  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns (max.)  
Industrial:9ns (max.)  
Full synchronous operation on both ports  
– 4ns setup to clock and 0ns hold on all control, data, and  
address inputs  
Data input, address, and control registers  
– Fast 7.5ns clock to data out in the Pipelined output mode  
– Self-timed write allows fast cycle time  
Low-power operation  
IDT709389L  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Active: 1.2W (typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Functional Block Diagram  
R/  
W
L
L
R/  
W
R
R
UB  
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
L
LB  
OE  
R
R
1b 0b  
0a 1a  
1a 0a  
a
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
FT/PIPE  
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
I/O  
Control  
I/O  
Control  
A
15R  
A
15L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
L
L
L
CLK  
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
R
L
CNTRST  
R
4844 drw 01  
NOVEMBER 2001  
1
DSC-4844/4  
©2001IntegratedDeviceTechnology,Inc.  

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