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709279L12GI PDF预览

709279L12GI

更新时间: 2024-10-27 20:36:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
18页 192K
描述
Application Specific SRAM, 32KX16, 12ns, CMOS, CPGA108, PGA-108

709279L12GI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:PGA-108
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:12 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):50 MHzI/O 类型:COMMON
JESD-30 代码:X-CPGA-P108JESD-609代码:e0
内存密度:524288 bit内存集成电路类型:APPLICATION SPECIFIC SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:108
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX16
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA108,12X12
封装形状:UNSPECIFIED封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
最大待机电流:0.005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.34 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30Base Number Matches:1

709279L12GI 数据手册

 浏览型号709279L12GI的Datasheet PDF文件第2页浏览型号709279L12GI的Datasheet PDF文件第3页浏览型号709279L12GI的Datasheet PDF文件第4页浏览型号709279L12GI的Datasheet PDF文件第5页浏览型号709279L12GI的Datasheet PDF文件第6页浏览型号709279L12GI的Datasheet PDF文件第7页 
HIGH-SPEED 32/16K x 16  
SYNCHRONOUS  
IDT709279/69S/L  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 4ns setup to clock and 1ns hold on all control, data, and  
addressinputs  
access of the same memory location  
High-speed clock to data access  
– Commercial:6.5/7.5/9/12/15ns(max.)  
Industrial:12ns (max.)  
Low-power operation  
Data input, address, and control registers  
IDT709279/69S  
Active:950mW(typ.)  
Standby: 5mW (typ.)  
IDT709279/69L  
Active:950mW(typ.)  
Standby: 1mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pin  
Counter enable and reset features  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
FunctionalBlockDiagram  
R/W  
R
R/W  
L
UBR  
UBL  
CE0L  
CE1L  
CE0R  
CE1R  
1
1
0
0
0/1  
0/1  
LB  
OE  
R
LB  
OE  
L
R
L
1a 0a  
1b 0b  
0a 1a  
0b 1b  
b
FT/PIPE  
L
0/1  
b
a
0/1  
a
FT/PIPE  
R
,
,
I/O8L  
I/O15L  
-
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0L-I/O7L  
I/O0R-I/O7R  
(1)  
(1)  
A
14R  
0R  
A
14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
MEMORY  
ARRAY  
A
0L  
CLK  
ADS  
CNTEN  
R
CLK  
ADS  
CNTEN  
L
L
L
R
R
CNTRST  
L
CNTRST  
R
3243 drw 01  
NOTE:  
1. A14X is a NC for IDT709269.  
JANUARY 2009  
1
DSC-3243/14  
©2009IntegratedDeviceTechnology,Inc.  

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