Datasheet > 7027S55GG

7027S55GG

更新时间： 2024-10-28 00:47:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	690K
描述
HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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7027S55GG 数据手册

HIGH-SPEED

IDT7027S/L

32K x 16 DUAL-PORT

STATIC RAM

Features

◆

IDT7027 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

High-speed access

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25ns (max.)

◆

Busy and Interrupt Flags

Low-power operation

On-chip port arbitration logic

– IDT7027S

Full on-chip hardware support of semaphore signaling

between ports

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7027L

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin

Ceramic Pin Grid Array (PGA)

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆

Separate upper-byte and lower-byte control for bus

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

matching capability.

◆

Dual chip enables allow for depth expansion without

external logic

Green parts available, see ordering information

FunctionalBlockDiagram

R/W

UBR

CE0L

CE0R

CE1L

CE1R

LBR

I/O ^8-15L

I/O8-15R

I/O0-7R

I/O

Control

I/O

Control

0-7L

I/O

(1,2)

BUSY

32Kx16

14L

14R

Address

Decoder

Address

Decoder

MEMORY

ARRAY

7027

14L

14R

CE0R

CE0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE1L

CE1R

R/W

R/WR

SEM

INT

SEM

(2)

INT

M/S⁽²⁾

NOTES:

3199 drw 01

1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

AUGUST 2015

DSC 3199/10

12 3 4 5 6 7...20

中文翻译

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