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7026S55JGI PDF预览

7026S55JGI

更新时间: 2024-11-08 19:17:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 679K
描述
Dual-Port SRAM, 16KX16, 55ns, CMOS, PQCC84, 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-84

7026S55JGI 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:compliantHTS代码:8542.32.00.41
风险等级:5.63最长访问时间:55 ns
JESD-30 代码:S-PQCC-J84内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端子数量:84
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX16
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子位置:QUADBase Number Matches:1

7026S55JGI 数据手册

 浏览型号7026S55JGI的Datasheet PDF文件第2页浏览型号7026S55JGI的Datasheet PDF文件第3页浏览型号7026S55JGI的Datasheet PDF文件第4页浏览型号7026S55JGI的Datasheet PDF文件第5页浏览型号7026S55JGI的Datasheet PDF文件第6页浏览型号7026S55JGI的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7026S/L  
16K X 16 DUAL-PORT  
STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
IDT7026 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
– Commercial: 15/20/25/35/55ns (max.)  
– Industrial: 20/25/35/55ns (max.)  
– Military: 20/25/35/55ns (max.)  
Low-power operation  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
– IDT7026S  
Active: 750mW (typ.)  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA and 84-pin PLCC  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Standby: 5mW (typ.)  
– IDT7026L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multi-  
plexed bus compatibility  
Green parts available, see ordering information  
FunctionalBlockDiagram  
R/  
W
UB  
R
R
R/  
W
UBL  
L
LB  
CE  
OE  
L
LB  
CER  
OE  
R
L
L
R
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1,2)  
L
(1,2)  
BUSY  
R
BUSY  
A
13R  
A
13L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
A
0L  
14  
14  
ARBITRATION  
SEMAPHORE  
LOGIC  
CEL  
CER  
SEM  
L
SEMR  
M/S  
2939 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs are non-tri-stated push-pull.  
AUGUST 2015  
1
DSC 2939/14  
©2015 Integrated Device Technology, Inc.  

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