Datasheet > 7025L15PFGI8

7025L15PFGI8

更新时间： 2022-05-14 22:07:41

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	201K
描述
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

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数据手册

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7025L15PFGI8 数据手册

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

ACE

(4)

tAOE

(4)

ABE

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

BUSYOUT

(2)

tHZ

(3,4)

2683 drw 07

BDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

tPU

tPD

50%

2683 drw 08

6.1402

1...7 8 91011 12 13...22

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