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7024S35PFB PDF预览

7024S35PFB

更新时间: 2024-11-02 20:53:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 190K
描述
Dual-Port SRAM, 4KX16, 35ns, CMOS, PQFP100, TQFP-100

7024S35PFB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.05
最长访问时间:35 ns其他特性:4K X 16 DUAL PORT SRAM
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:4KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:1.6 mm最大待机电流:0.00003 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.3 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

7024S35PFB 数据手册

 浏览型号7024S35PFB的Datasheet PDF文件第2页浏览型号7024S35PFB的Datasheet PDF文件第3页浏览型号7024S35PFB的Datasheet PDF文件第4页浏览型号7024S35PFB的Datasheet PDF文件第5页浏览型号7024S35PFB的Datasheet PDF文件第6页浏览型号7024S35PFB的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7024S/L  
4K x 16 DUAL-PORT  
STATIC RAM  
IDT7024 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin  
Quad Flatpack  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:20/25/35/55/70ns(max.)  
Industrial:55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
IDT7024S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7024L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
bus compatibility  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
LBL  
CEL  
OEL  
R
CER  
OER  
LB  
I/O8L-I/O15L  
I/O8R-I/O15R  
I/O  
I/O  
Control  
Control  
I/O0L-I/O7L  
0R  
I/O -I/O  
7R  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A11R  
A0R  
A11L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
12  
12  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CER  
OER  
CEL  
OE  
L
WR  
R/  
R/WL  
SEMR  
(2)  
SEML  
(2)  
M/S  
INTR  
2740 drw 01  
INTL  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
APRIL 2000  
1
DSC 2740/10  
©2000IntegratedDeviceTechnology,Inc.  

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