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7016S20JGI8 PDF预览

7016S20JGI8

更新时间: 2024-11-20 18:23:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 346K
描述
Dual-Port SRAM, 16KX9, 20ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68

7016S20JGI8 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:compliant风险等级:5.75
最长访问时间:20 nsJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.2062 mm
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9功能数量:1
端子数量:68字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX9封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
座面最大高度:4.57 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:24.2062 mm
Base Number Matches:1

7016S20JGI8 数据手册

 浏览型号7016S20JGI8的Datasheet PDF文件第2页浏览型号7016S20JGI8的Datasheet PDF文件第3页浏览型号7016S20JGI8的Datasheet PDF文件第4页浏览型号7016S20JGI8的Datasheet PDF文件第5页浏览型号7016S20JGI8的Datasheet PDF文件第6页浏览型号7016S20JGI8的Datasheet PDF文件第7页 
HIGH-SPEED  
16K X 9 DUAL-PORT  
STATIC RAM  
IDT7016S/L  
IDT7016 easily expands data bus width to 18 bits or  
Features  
more using the Master/Slave select when cascading  
more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in ceramic 68-pin PGA, 68-pin PLCC, and an  
80-pin TQFP  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Green parts available, see ordering information  
True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
High-speed access  
– Commercial:12/15/20/25/35ns (max.)  
– Industrial: 20ns (max.)  
– Military: 20/25/35ns (max.)  
Low-power operation  
– IDT7016S  
Active: 750mW (typ.)  
Standby: 5mW (typ.)  
– IDT7016L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
OEL  
OER  
CER  
CEL  
R/WR  
R/W  
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
BUSY  
R
A
13L  
A
13R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0L  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(2)  
(2)  
INTL  
INT  
R
3190 drw 01  
NOTES:  
1. In MASTER mode: BUSY is an output and is a push-pull driver  
InSLAVEmode:BUSYisinput.  
2. BUSYoutputsandINToutputsarenon-tri-statedpush-pulldrivers.  
OCTOBER2014  
1
©2014 Integrated Device Technology, Inc.  
DSC 3190/11  

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