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7016L15G

更新时间: 2024-11-20 10:40:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 164K
描述
PGA-68, Tray

7016L15G 数据手册

 浏览型号7016L15G的Datasheet PDF文件第2页浏览型号7016L15G的Datasheet PDF文件第3页浏览型号7016L15G的Datasheet PDF文件第4页浏览型号7016L15G的Datasheet PDF文件第5页浏览型号7016L15G的Datasheet PDF文件第6页浏览型号7016L15G的Datasheet PDF文件第7页 
HIGH-SPEED  
16K X 9 DUAL-PORT  
STATIC RAM  
IDT7016S/L  
IDT7016 easily expands data bus width to 18 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:12/15/20/25/35ns(max.)  
Industrial:20ns (max.)  
Busy and Interrupt Flag  
On-chip port arbitration logic  
Military:20/25/35ns(max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-  
pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
IDT7016S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7016L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
FunctionalBlockDiagram  
OEL  
OER  
CER  
CEL  
R/WR  
R/W  
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
13L  
A
13R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0L  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(2)  
(2)  
INTL  
INT  
R
3190 drw 01  
NOTES:  
1. In MASTER mode: BUSY is an output and is a push-pull driver  
In SLAVE mode: BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.  
JANUARY 2009  
1
©2009 IntegratedDeviceTechnology,Inc.  
DSC 3190/10  

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