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7007S25G8

更新时间: 2024-10-27 09:12:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 164K
描述
Multi-Port SRAM, 32KX8, 25ns, CMOS, CPGA68

7007S25G8 数据手册

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HIGH-SPEED  
IDT7007S/L  
32K x 8 DUAL-PORT  
STATIC RAM  
Features  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:25/35/55ns(max.)  
Industrial:20/25/35/55ns(max.)  
– Commercial:15/20/25/35/55ns(max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7007S  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA and PLCC and a 80-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:850mW(typ.)  
Standby: 5mW (typ.)  
IDT7007L  
Active:850mW(typ.)  
Standby: 1mW (typ.)  
IDT7007 easily expands data bus width to 16 bits or more  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CEL  
CER  
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
(1,2)  
BUSY (1,2)  
L
BUSY  
R
A
14R  
0R  
A
14L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
OE  
R
R
R/W  
L
SEM  
R
SEM  
L
M/S  
(2)  
(2)  
INT  
R
INTL  
2940 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY and INT outputs are non-tri-stated push-pull.  
JANUARY 2006  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC 2940/12  

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