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7007S15JG8 PDF预览

7007S15JG8

更新时间: 2024-10-26 17:52:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 164K
描述
Multi-Port SRAM, 32KX8, 15ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68

7007S15JG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:QCCJ, PGA68,11X11
Reach Compliance Code:compliantECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.44
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e3
内存密度:262144 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:68字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:PGA68,11X11封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.015 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.325 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:2.54 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

7007S15JG8 数据手册

 浏览型号7007S15JG8的Datasheet PDF文件第2页浏览型号7007S15JG8的Datasheet PDF文件第3页浏览型号7007S15JG8的Datasheet PDF文件第4页浏览型号7007S15JG8的Datasheet PDF文件第5页浏览型号7007S15JG8的Datasheet PDF文件第6页浏览型号7007S15JG8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7007S/L  
32K x 8 DUAL-PORT  
STATIC RAM  
Features  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:25/35/55ns(max.)  
Industrial:20/25/35/55ns(max.)  
– Commercial:15/20/25/35/55ns(max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7007S  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA and PLCC and a 80-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:850mW(typ.)  
Standby: 5mW (typ.)  
IDT7007L  
Active:850mW(typ.)  
Standby: 1mW (typ.)  
IDT7007 easily expands data bus width to 16 bits or more  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CEL  
CER  
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
(1,2)  
BUSY (1,2)  
L
BUSY  
R
A
14R  
0R  
A
14L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
OE  
R
R
R/W  
L
SEM  
R
SEM  
L
M/S  
(2)  
(2)  
INT  
R
INTL  
2940 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY and INT outputs are non-tri-stated push-pull.  
JANUARY 2006  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC 2940/12  

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