Datasheet > 635L6I3FREQ

635L6I3FREQ

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
西迪斯 - CTS		/
页数	文件大小	规格书
4页	153K
描述
LVDS Output Clock Oscillator, 19.44MHz Min, 250MHz Max, GREEN, CERAMIC PACKAGE-6

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635L6I3FREQ 数据手册

Model 635

7.5x5.0mm Low Cost

LVPECL or LVDS Clock Oscillator

ELECTRICAL CHARACTERISTICS

PARAMETER

Maximum Supply Voltage

Storage Temperature

SYMBOL

V_CC

T_STG

CONDITIONS

MIN

-0.5

-55

TYP

MAX

5.0

125

UNIT

°C

Frequency Range (See Note 1)

LVPECL and LVDS

f_O

MHz

19.44

250

20, 25, 50

or 100

Frequency Stability

(See Note 2 and Ordering Information)

∆f/f_O

± ppm

Operating Temperature

Commercial

Industrial

T_A

V_CC

I_CC

°C

-20

-40

2.38

3.14

2.63

3.47

2.5

3.3

Supply Voltage

± 5 %

Supply Current

LVPECL

LVDS

Start Up Time

Phase Jitter

Period Jitter

Maximum Load

100

T_S

tjrms

pjrms

Application of V_CC

ps RMS

Bandwidth 12 kHz - 20 MHz

Enable Function

Enable Input Voltage

Disable Input Voltage

Disable Current

Enable Time

Standby

V_IH

V_IL

I_IL

0.7*V_CC

Pin 1 or Pin 2 Logic '1', Output Enabled

Pin 1 or Pin 2 Logic '0', Output Disabled

Pin 1 or Pin 2 Logic '1' , Output Disabled

Pin 1 or Pin 2 Logic '1'

0.3*V_CC

T_PLZ

LVPECL WAVEFORM

R_L

SYM

Ohms

Output Load

@ V_CC- 1.3V

Output Duty Cycle

Output Voltage Levels

Logic '1' Level

V_OH

V_OL

V_CC- 1.025V

PECL Load

V_CC- 1.62V

Logic '0' Level

Rise and Fall Time

f_O< 100 MHz

f_O> 100 MHz

T_R, T_F

@ 20% - 80% Levels

0.8

0.5

1.0

0.6

LVDS WAVEFORM

R_L

SYM

V_OD

V_OS

Between Outputs

@ 1.25V

RL = 100 Ohms

247

1.125

100

454

1.375

Ohms

Output Load

Output Duty Cycle

Differential Output Voltage

Differential Output Error

Offset Voltage

350

1.25

LVDS Load

Offset Error

Output Voltage Levels

Logic '1' Level

Logic '0' Level

V_OH

V_OL

LVDS Load

0.9

1.43

1.1

1.6

Rise and Fall Time

f_O< 100 MHz

T_R, T_F

@ 20% - 80% Levels

0.8

0.5

1.0

0.6

f_O> 100 MHz

Notes:

1. For frequencies above 160 MHz consult factory for availability.

2. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.

PECL/LVDS OUTPUT WAVEFORM

VOH

VOS

OUT

80%

50%

20%

ENABLE TRUTH TABLE

PIN 1 or PIN 2 PIN 4 / PIN 5

OUT

Logic ‘1’

Open

Output

VOL

UPTIME (t)

Logic ‘0’

High Imp.

PERIOD (T)

DUTY CYCLE = t/T x 100 (%)

Document No. 008-0284-0

Page 2 - 4

Rev. D

CTS Electronic Components, Inc.

171 Covington Drive

Bloomingdale, IL 60108

123 4

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