Datasheet > 5V991A-2JG

5V991A-2JG

更新时间： 2024-02-17 20:36:52

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
8页	98K
描述
PLCC-32, Tube

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5V991A-2JG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	PLCC
包装说明：	QCCJ, LDCC32,.5X.6	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.79
系列：	5V	输入调节：	STANDARD
JESD-30 代码：	R-PQCC-J32	JESD-609代码：	e3
长度：	13.97 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.012 A	湿度敏感等级：	1
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	4
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC32,.5X.6	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.25 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.5 ns
座面最大高度：	3.429 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	11.43 mm	最小 fmax：	85 MHz
Base Number Matches：	1

5V991A-2JG 数据手册

IDT5V991A

COMMERCIAL AND INDUSTRIAL TEMPERATURE

RANGES

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

EXTERNAL FEEDBACK

By providing external feedback, the IDT5V991A gives users flex-

ibility with regard to skew adjustment. The FB signal is compared

with the input REF signal at the phase detector in order to drive the

VCO. Phase differences cause the VCO of the PLL to adjust upwards

or downwards accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing ac-

curate responses to input frequency changes.

PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

FS = LOW

1/(44 x FNOM)

15 to 35MHz

FS = MID

1/(26 x FNOM)

25 to 60MHz

FS = HIGH

1/(16 x FNOM)

40 to 85 MHz

Comments

Timing Unit Calculation (tU)

VCO Frequency Range (FNOM)^(1,2)

Skew Adjustment Range⁽³⁾

Max Adjustment:

±9.09ns

±49º

±9.23ns

±83º

±9.38ns

±135º

Phase Degrees

% of Cycle Time

±14%

±23%

±37%

Example 1, FNOM = 15MHz

Example 2, FNOM = 25MHz

Example 3, FNOM = 30MHz

Example 4, FNOM = 40MHz

Example 5, FNOM = 50MHz

Example 6, FNOM = 80MHz

tU = 1.52ns

tU = 0.91ns

tU = 0.76ns

—

tU = 1.54ns

tU = 1.28ns

tU = 0.96ns

tU = 0.77ns

—

tU = 1.56ns

tU = 1.25ns

tU = 0.78ns

—

NOTES:

1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input

frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher

outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided.

The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed

output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and

4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0

LL⁽¹⁾

Skew (Pair #1, #2)

Skew (Pair #3)

Divide by 2

–6tU

Skew (Pair #4)

Divide by 2

–6tU

–4tU

–3tU

–2tU

–4tU

–1tU

–2tU

Zero Skew

1tU

Zero Skew

2tU

Zero Skew

2tU

4tU

3tU

6tU

Inverted⁽²⁾

4tU

Divide by 4

NOTES:

1. LL disables outputs if TEST = MID and GND/sOE = HIGH.

2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW.

1 234 5 6 7 8

下载PDF

与5V991A-2JG相关器件

型号	品牌	描述	获取价格	数据表
5V991A-2JG8	IDT	PLCC-32, Reel	获取价格
5V991A-2JGI	IDT	PLCC-32, Tube	获取价格
5V991A-2JGI8	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, GREEN,	获取价格
5V991A-5J	IDT	PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC	获取价格
5V991A-5JG	IDT	PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, GREEN,	获取价格
5V991A-5JG8	IDT	PLL Based Clock Driver	获取价格

与5V991A-2JG相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

7
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

7
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

10
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

5

产品中心

服务支持

精选活动

关于我们

帮助中心

5V991A-2JG

5V991A-2JG 技术参数

5V991A-2JG 数据手册

与5V991A-2JG相关器件

与5V991A-2JG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

5V991A-2JG

5V991A-2JG 技术参数

5V991A-2JG 数据手册

与5V991A-2JG相关器件

与5V991A-2JG相关文章

您还可以找

您在本页遇到什么问题？