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5V926APGGI PDF预览

5V926APGGI

更新时间: 2024-01-25 00:46:58
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 94K
描述
TSSOP-16, Tube

5V926APGGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, TSSOP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:160 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:40 MHz认证状态:Not Qualified
子类别:Clock Generators最大压摆率:50 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

5V926APGGI 数据手册

 浏览型号5V926APGGI的Datasheet PDF文件第2页浏览型号5V926APGGI的Datasheet PDF文件第3页浏览型号5V926APGGI的Datasheet PDF文件第4页浏览型号5V926APGGI的Datasheet PDF文件第5页浏览型号5V926APGGI的Datasheet PDF文件第6页 
Single Output Clock Generator  
IDT5V926A  
DATA SHEET  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014  
FEATURES:  
DESCRIPTION:  
• 3V to 3.6V operating voltage  
The IDT5V926A is a low-cost, low skew, low jitter, and  
high-performance clock multiplier with a reference clock  
from either a lower frequency crystal or clock input. It has  
been specially designed to interface with Gigabit Ethernet  
and Fast Ethernet applications by providing a 125MHz  
clock from 25MHz input. It can be programmed to provide  
output frequencies ranging from 48MHz to 160MHz, with  
input frequencies ranging from 6MHz to 80MHz.  
The IDT5V926A includes an internal RC filter that pro-  
vides excellent jitter characteristics and eliminates the  
need for external components. When using the optional  
crystal input, the device accepts a 10 - 40MHz fundamental  
mode crystal with a maximum equivalent series resistance  
of 50Ω.  
• 48MHz to 160MHz output frequency range  
• Input from fundamental crystal oscillator or external  
source  
• Internal PLL feedback (loading the feedback output  
relative to the other outputs, will adjust the propagation  
delay between REF inputs and outputs)  
• Select inputs (S[1:0]) for FB divide selection (multiply  
ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8)  
• Low jitter  
• PLL bypass for testing and power-down control  
(S1 = H, S0 = H, powers part down <500µA)  
• Available in TSSOP package  
• Pin and function compatible to IDT5V926  
• Use replacement parts: 840004AG or  
8T49004A-dddNLGI  
APPLICATIONS:  
• Gigabit ethernet  
• Router  
• Network switches  
• SAN  
• Instrumentation  
• Fibre channel  
FUNCTIONAL BLOCK DIAGRAM  
OE  
VCO DIVIDE  
1/N  
PHASE  
DETECTOR  
CHARGE  
PUMP  
LOOP  
FILTER  
VCO  
QOUT  
0
1
X1/REF  
CRYSTAL  
OSCILLATOR  
QREF  
X2  
SELECT MODE  
S1 S0  
REFE  
IDT5V926A REVISION B DECEMBER 18, 2013  
1
©2013 Integrated Device Technology, Inc.  

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