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5V49EE502 PDF预览

5V49EE502

更新时间: 2024-02-12 23:14:04
品牌 Logo 应用领域
艾迪悌 - IDT 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
34页 386K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

5V49EE502 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:VFQFPN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.52
Samacsys Description:VFQFP-N 4MM X 4MM X 0.9 MM MM- NO LEAD系列:5V
输入调节:MUXJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:24实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.075 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
最小 fmax:500 MHzBase Number Matches:1

5V49EE502 数据手册

 浏览型号5V49EE502的Datasheet PDF文件第1页浏览型号5V49EE502的Datasheet PDF文件第2页浏览型号5V49EE502的Datasheet PDF文件第3页浏览型号5V49EE502的Datasheet PDF文件第5页浏览型号5V49EE502的Datasheet PDF文件第6页浏览型号5V49EE502的Datasheet PDF文件第7页 
5V49EE502  
EEPROM PROGRAMMABLE CLOCK GENERATOR  
Pin#  
17  
Pin Name  
OUT3  
I/O  
Pin Type  
Adjustable1  
Power  
Pin Description  
O
Configurable clock output 3.  
18  
Device power supply. Connect to 1.8 to 3.3V. Sets output voltage  
levels for OUT3 and OUT6.  
VDDO3  
19  
20  
21  
22  
SEL2  
SEL1  
I
I
I
I
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Configuration select pin. Weak internal pull down resistor.  
Configuration select pin. Weak internal pull down resistor.  
Configuration select pin. Weak internal pull down resistor.  
SEL0  
SD/OE  
Enables/disables the outputs or powers down the chip. The SP bit  
(0x02) controls the polarity of the signal to be either active HIGH or  
LOW. (Default is active LOW.) Weak internal pull down resistor.  
23  
24  
OUT0  
GND  
O
Adjustable1  
Power  
Configurable clock output 0.  
Connect to Ground.  
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels  
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.  
3. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.  
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.  
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR  
4
5V49EE502  
JUNE 18, 2018  

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