5V49EE702NDGI8

更新时间： 2024-11-24 12:50:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
34页	702K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

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5V49EE702NDGI8 数据手册

DATASHEET

EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE702

Description

Features:

The IDT5V49EE702 is a programmable clock generator

intended for high performance data-communications,

telecommunications, consumer, and networking

applications. There are four internal PLLs, each individually

programmable, allowing for four unique non-integer-related

frequencies. The frequencies are generated from a single

reference clock. The reference clock can come from one of

the two redundant clock inputs. A glitchless automatic or

manual switchover function allows any one of the redundant

clocks to be selected during normal operation.

• Four internal PLLs

• Internal non-volatile EEPROM

• Fast (400kHz) mode I C serial interface

• Input frequency range: 1 MHz to 200 MHz

• Output frequency range: 4.9 kHz to 500 MHz

• Reference crystal input with programmable linear load

capacitance

– Crystal frequency range: 8 MHz to 50 MHz

The IDT5V49EE702 is in-system, programmable and can

be programmed through the use of I C interface. An

internal EEPROM allows the user to save and restore the

configuration of the device without having to reprogram it on

power-up.

• Three independently controlled VDDO (1.8V - 3.3V)

• Each PLL has a 7-bit reference divider and a 12-bit

feedback-divider

• 8-bit output-divider blocks

• Fractional division capability on one PLL

Each of the four PLLs has an 7-bit reference divider and a

12-bit feedback divider. This allows the user to generate

four unique non-integer-related frequencies. The PLL loop

bandwidth is programmable to allow the user to tailor the

PLL response to the application. For instance, the user can

tune the PLL parameters to minimize jitter generation or to

maximize jitter attenuation. Spread spectrum generation

and/or fractional divides are allowed on two of the PLLs.

• Two of the PLLs support spread spectrum generation

capability

• I/O Standards:

– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS

– Outputs - LVPECL, LVDS and HCSL

– Inputs - 3.3 V LVTTL/ LVCMOS

• Programmable slew rate control

• Programmable loop bandwidth

• Programmable output inversion to reduce bimodal jitter

There are a total of five 8-bit output dividers. Each output

bank can be configured to support LVTTL, LVPECL, LVDS

or HCSL logic levels. Out0 (Output 0) supports LVTTL

standard only. The outputs are connected to the PLLs via a

switch matrix. The switch matrix allows the user to route the

PLL outputs to any output bank. This feature can be used to

simplify and optimize the board layout. In addition, each

output's slew rate and enable/disable function is

programmable.

• Redundant clock inputs with glitchless auto and manual

switchover options

• Individual output enable/disable

• Power-down mode

• 3.3V core V

• Available in VFQFPN package

• -40 to +85 C Industrial Temp operation

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE702 REV F 022310

12 3 4 5 6 7...34

中文翻译

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5V49EE702NDGI8 替代型号

型号	品牌	替代类型	描述	数据表
5V49EE702NDGI	IDT	完全替代	EEPROM PROGRAMMABLE CLOCK GENERATOR

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