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5V19EE903PGGI8 PDF预览

5V19EE903PGGI8

更新时间: 2024-10-29 01:07:43
品牌 Logo 应用领域
艾迪悌 - IDT 可编程只读存储器电动程控只读存储器电可擦编程只读存储器驱动光电二极管逻辑集成电路石英晶振压控振荡器
页数 文件大小 规格书
31页 369K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

5V19EE903PGGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.76
系列:5V输入调节:MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:7最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:200 MHz
Base Number Matches:1

5V19EE903PGGI8 数据手册

 浏览型号5V19EE903PGGI8的Datasheet PDF文件第5页浏览型号5V19EE903PGGI8的Datasheet PDF文件第6页浏览型号5V19EE903PGGI8的Datasheet PDF文件第7页浏览型号5V19EE903PGGI8的Datasheet PDF文件第9页浏览型号5V19EE903PGGI8的Datasheet PDF文件第10页浏览型号5V19EE903PGGI8的Datasheet PDF文件第11页 
IDT5V19EE903  
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
CLOCK SYNTHESIZER  
if 1 < Amplitude < 2, then set X2 bit to '1'.  
SS_OFFSET[5:0]  
These bits are used to program the fractional offset with  
respect to the nominal M integer value. For center spread,  
the SS_OFFSET is set to '0' so that the spread spectrum  
waveform is centered about the nominal M (Mnom) value.  
For down spread, the SS_OFFSET > '0' such the spread  
spectrum waveform is centered about the (Mideal -1  
+SS_Offset) value. The downspread percentage can be  
thought of in terms of center spread. For example, a  
downspread of -1% can also be considered as a center  
spread of 0.5% but with Mnom shifted down by one and  
offset. The SS_OFFSET has integer values ranging from 0  
to 63.  
Modulation frequency:  
FPFD = FIN / D (Eq. 6)  
FVCO = FPFD * MNOM (Eq. 7)  
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)  
Spread:  
Σ∆ = SD0 + SD1 + SD2 + + SD11  
the number of samples used depends on the NSSC value  
Σ∆< 63 - SS_OFFSET  
SD[3:0]  
These bits are used to shape the profile of the spread  
spectrum waveform. These are delta-encoded samples of  
the waveform. There are twelve sets of SD samples. The  
NSSC bits determine how many of these samples are used  
for the waveform. The sum of these delta-encoded samples  
(sigma delta- encoded samples) determine the amount of  
spread and should not exceed (63 - SS_OFFSET). The  
maximum spread is inversely proportional to the nominal M  
integer value.  
Spread% = (Σ∆ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)  
Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)  
DITH  
This bit is used for dithering the sigma-delta-encoded  
samples. This will randomize the least-significant bit of the  
input to the spread spectrum modulator. Set the bit to '1' to  
enable dithering.  
X2  
This bit will double the total value of the  
sigma-delta-encoded-samples which will increase the  
amplitude of the spread spectrum waveform by a factor of  
two. When X2 is '0', the amplitude remains nominal but if set  
to '1', the amplitude is increased by x2. The following  
equations govern how the spread spectrum is set:  
TSSC = TSSC[3:0] + 2 (Eq. 2)  
NSSC = NSSC[2:0] * 2 (Eq. 3)  
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)  
where SJ is the unencoded sample out of a possible 12 and  
SDK is the delta-encoded sample out of a possible 12.  
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2  
(Eq. 5)  
IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
8
IDT5V19EE903 REV N 092412  

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