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5P49EE502NDGI8 PDF预览

5P49EE502NDGI8

更新时间: 2024-01-06 13:55:39
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
26页 233K
描述
VERSACLOCK? LOW POWER CLOCK GENERATOR IDT5P49EE502

5P49EE502NDGI8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Not Recommended零件包装代码:VFQFPN
包装说明:HVQCCN, LCC20,.11SQ,16针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:11129317Samacsys Pin Count:21
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:NDG20P2*Samacsys Released Date:2020-01-28 12:12:00
Is Samacsys:NJESD-30 代码:S-XQCC-N20
JESD-609代码:e3长度:3 mm
湿度敏感等级:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:120 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC20,.11SQ,16
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:1.8 V
主时钟/晶体标称频率:40 MHz认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Generators
最大供电电压:1.98 V最小供电电压:1.62 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

5P49EE502NDGI8 数据手册

 浏览型号5P49EE502NDGI8的Datasheet PDF文件第7页浏览型号5P49EE502NDGI8的Datasheet PDF文件第8页浏览型号5P49EE502NDGI8的Datasheet PDF文件第9页浏览型号5P49EE502NDGI8的Datasheet PDF文件第11页浏览型号5P49EE502NDGI8的Datasheet PDF文件第12页浏览型号5P49EE502NDGI8的Datasheet PDF文件第13页 
IDT5P49EE502  
VERSACLOCK® LOW POWER CLOCK GENERATOR  
EEPROM CLOCK GENERATOR  
External I2C Interface Condition  
after the STOP condition is issued by the Master, during  
which time the IDT5P49EE502 will not generate  
EEPROM Interface  
The IDT5P49EE502 can store its configuration in an internal  
EEPROM. The contents of the device's internal  
programming registers can be saved to the EEPROM by  
issuing a save instruction (ProgSave) and can be loaded  
back to the internal programming registers by issuing a  
restore instruction (ProgRestore).  
Acknowledge bits. The IDT5P49EE502 will acknowledge  
the instructions after it has completed execution of them.  
2
During that time, the I C bus should be interpreted as busy  
by all other users of the bus.  
On power-up of the IDT5P49EE502, an automatic restore is  
performed to load the EEPROM contents into the internal  
programming registers. The IDT5P49EE502 will be ready to  
accept a programming instruction once it acknowledges its  
2
To initiate a save or restore using I C, only two bytes are  
transferred. The Device Address is issued with the  
read/write bit set to “0”, followed by the appropriate  
command code. The save or restore instruction executes  
2
7-bit I C address.  
Progwrite  
Progwrite Command Frame  
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.  
®
IDT® VERSACLOCK LOW POWER CLOCK GENERATOR  
10  
IDT5P49EE502  
REV D 072610  

5P49EE502NDGI8 替代型号

型号 品牌 替代类型 描述 数据表
5P49EE502NDGI IDT

完全替代

VERSACLOCK? LOW POWER CLOCK GENERATOR IDT5P49EE502

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