Datasheet > 5P49V5901A045NLGI

5P49V5901A045NLGI

更新时间： 2024-02-28 12:56:29

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
37页	435K
描述
Clock Generator, PQCC24

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5P49V5901A045NLGI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	S-PQCC-N24	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	1.8/3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	47 mA	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

5P49V5901A045NLGI 数据手册

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Programmable Clock Generator

5P49V5901A

DATASHEET

Description

Features

The 5P49V5901A is a programmable clock generator

intended for high performance consumer, networking,

industrial, computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to four independent output frequencies

• High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

Programmable (OTP) memory or changed using I C

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock 5).

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

• Four fractional output dividers (FODs)

• Independent Spread Spectrum capability on each output

pair

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

• I C serial programming interface

• One reference LVCMOS output clock

• Four universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

The device may be configured to use one of two I C

• I/O Standards:

addresses to allow multiple devices to be used in a system.

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os - LVPECL, LVDS and HCSL

Pin Assignment

• Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

• Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

24 23 22 21 20 19

V_DDO

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

CLKIN

CLKINB

XOUT

OUT2

• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

OUT2B

EPAD

V_DDO3

XIN/REF

V_DDA

• Redundant clock inputs with manual switchover

• Programmable loop bandwidth

• Programmable output to output skew

• Programmable slew rate control

• Programmable crystal load capacitance

• Individual output enable/disable

• Power-down mode

OUT3

OUT3B

CLKSEL

10 11 12

• 1.8V, 2.5V or 3.3V core V

, V

DDA

DDD

24-pin VFQFPN

• Available in 24-pin VFQFPN 4mm x 4mm package

• -40° to +85°C industrial temperature operation

5P49V5901A REVISION F 03/10/15

12 3 4 5 6 7...37

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