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5P49V5901

更新时间: 2022-02-26 13:31:05
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
37页 451K
描述
Programmable Clock Generator

5P49V5901 数据手册

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Programmable Clock Generator  
5P49V5901  
DATASHEET  
Description  
Features  
The 5P49V5901 is a programmable clock generator intended  
for high performance consumer, networking, industrial,  
computing, and data-communications applications.  
Configurations may be stored in on-chip One-Time  
Generates up to four independent output frequencies  
High performance, low phase noise PLL, <0.7 ps RMS  
typical phase jitter on outputs:  
2
– PCIe Gen1, 2, 3 compliant clock capability  
– USB 3.0 compliant clock capability  
– 1 GbE and 10 GbE  
Programmable (OTP) memory or changed using I C  
interface. This is IDTs fifth generation of programmable clock  
®
technology (VersaClock 5).  
The frequencies are generated from a single reference clock.  
The reference clock can come from one of the two redundant  
clock inputs. A glitchless manual switchover function allows  
one of the redundant clocks to be selected during normal  
operation.  
Four fractional output dividers (FODs)  
Independent Spread Spectrum capability on each output  
pair  
Four banks of internal non-volatile in-system  
programmable or factory programmable OTP memory  
Two select pins allow up to 4 different configurations to be  
programmed and accessible using processor GPIOs or  
bootstrapping. The different selections may be used for  
different operating modes (full function, partial function, partial  
power-down), regional standards (US, Japan, Europe) or  
system production margin testing.  
2
I C serial programming interface  
One reference LVCMOS output clock  
Four universal output pairs:  
– Each configurable as one differential output pair or two  
LVCMOS outputs  
2
The device may be configured to use one of two I C  
I/O Standards:  
addresses to allow multiple devices to be used in a system.  
– Single-ended I/Os: 1.8V to 3.3V LVCMOS  
– Differential I/Os - LVPECL, LVDS and HCSL  
Pin Assignment  
Input frequency ranges:  
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to  
200MHz  
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,  
CLKINB) – 1MHz to 350MHz  
– Crystal frequency range: 8MHz to 40MHz  
Output frequency ranges:  
– LVCMOS Clock Outputs – 1MHz to 200MHz  
24 23 22 21 20 19  
1
2
VDDO  
2
18  
17  
16  
– LVDS, LVPECL, HCSL Differential Clock Outputs –  
1MHz to 350MHz  
CLKIN  
CLKINB  
XOUT  
OUT2  
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for  
each output pair  
3
4
OUT2B  
EPAD  
VDDO3  
XIN/REF  
VDDA  
15  
14  
Redundant clock inputs with manual switchover  
Programmable loop bandwidth  
Programmable output to output skew  
Programmable slew rate control  
Programmable crystal load capacitance  
Individual output enable/disable  
Power-down mode  
5
6
OUT3  
13  
OUT3B  
CLKSEL  
8
9
10 11 12  
7
1.8V, 2.5V or 3.3V core V  
, V  
DDA  
DDD  
24-pin VFQFPN  
Available in 24-pin VFQFPN 4mm x 4mm package  
-40° to +85°C industrial temperature operation  
5P49V5901 NOVEMBER 11, 2016  
1
©2016 Integrated Device Technology, Inc.  

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