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5M240ZM100C4 PDF预览

5M240ZM100C4

更新时间: 2024-02-04 01:03:17
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟LTE可编程逻辑
页数 文件大小 规格书
30页 447K
描述
Flash PLD, 7.9ns, 192-Cell, CMOS, PBGA100, 6 X 6 MM, 0.50 MM PITCH, MBGA-100

5M240ZM100C4 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TFBGA, BGA100,11X11,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
其他特性:YES最大时钟频率:184.1 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B100
JESD-609代码:e1JTAG BST:YES
长度:6 mmI/O 线路数量:79
宏单元数:192端子数量:100
最高工作温度:85 °C最低工作温度:
组织:79 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA100,11X11,20封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8,1.2/3.3 V可编程逻辑类型:FLASH PLD
传播延迟:7.9 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Programmable Logic Devices
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:6 mm
Base Number Matches:1

5M240ZM100C4 数据手册

 浏览型号5M240ZM100C4的Datasheet PDF文件第2页浏览型号5M240ZM100C4的Datasheet PDF文件第3页浏览型号5M240ZM100C4的Datasheet PDF文件第4页浏览型号5M240ZM100C4的Datasheet PDF文件第6页浏览型号5M240ZM100C4的Datasheet PDF文件第7页浏览型号5M240ZM100C4的Datasheet PDF文件第8页 
Chapter 3: DC and Switching Characteristics for MAX V Devices  
3–5  
Operating Conditions  
Output Drive Characteristics  
Figure 3–1 shows the typical drive strength characteristics of MAX V devices.  
Figure 3–1. Output Drive Characteristics of MAX V Devices (Note 1)  
MAX V Output Drive IOH Characteristics  
(Maximum Drive Strength)  
MAX V Output Drive IOL Characteristics  
(Maximum Drive Strength)  
60  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
3.3-V VCCIO  
3.3-V VCCIO  
2.5-V VCCIO  
2.5-V VCCIO  
1.8-V VCCIO  
1.8-V VCCIO  
1.5-V VCCIO  
1.2-V VCCIO (2)  
1.5-V VCCIO  
1.2-V VCCIO (2)  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
Voltage (V)  
Voltage (V)  
MAX V Output Drive IOL Characteristics  
(Minimum Drive Strength)  
MAX V Output Drive IOH Characteristics  
(Minimum Drive Strength)  
30  
25  
20  
15  
10  
5
35  
3.3-V VCCIO  
3.3-V VCCIO  
30  
25  
20  
15  
10  
5
2.5-V VCCIO  
2.5-V VCCIO  
1.8-V VCCIO  
1.5-V VCCIO  
1.8-V VCCIO  
1.5-V VCCIO  
0
0
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
Voltage (V)  
Voltage (V)  
Notes to Figure 3–1:  
(1) The DC output current per pin is subject to the absolute maximum rating of Table 3–1 on page 3–1.  
(2) 1.2-V VCCIO is only applicable to the maximum drive strength.  
I/O Standard Specifications  
Table 3–5 through Table 3–13 on page 3–8 list the I/O standard specifications for the  
MAX V device family.  
Table 3–5. 3.3-V LVTTL Specifications for MAX V Devices  
Symbol  
VCCIO  
Parameter  
I/O supply voltage  
Conditions  
Minimum  
3.0  
Maximum  
3.6  
Unit  
V
VIH  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
1.7  
4.0  
V
VIL  
–0.5  
2.4  
0.8  
V
VOH  
IOH = –4 mA (1)  
IOL = 4 mA (1)  
V
VOL  
0.45  
V
Note to Table 3–5:  
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the  
MAX V Device Architecture chapter.  
May 2011 Altera Corporation  
MAX V Device Handbook  
 
 
 
 

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