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5CGTFD9E5F31C7N

更新时间： 2024-01-27 10:30:56
品牌 Logo 应用领域
英特尔 - INTEL 栅可编程逻辑
页数 文件大小 规格书
95页 1359K
描述
Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

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5CGTFD9E5F31C7N 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA, BGA896,30X30,40Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.6
JESD-30 代码：S-PBGA-B896JESD-609代码：e1
长度：31 mm湿度敏感等级：3
输入次数：448逻辑单元数量：301000
输出次数：448端子数量：896
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA896,30X30,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.1,1.2/3.3,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.13 V
最小供电电压：1.07 V标称供电电压：1.1 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：31 mmBase Number Matches：1

5CGTFD9E5F31C7N 数据手册

 浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第89页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第90页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第91页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第93页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第94页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第95页 
CV-51002  
2015.12.04  
92  
Document Revision History  
Date  
Version  
Changes  
•
•
Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:  
•
•
SPI Master Timing Requirements for Cyclone V Devices  
SPI Slave Timing Requirements for Cyclone V Devices  
Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM  
mode may not function properly with the USB controller due to a timing issue. It is recommended that  
designers use the MicroChip USB3300 PHY device that has been proven to be successful on the develop‐  
ment board.  
•
•
•
Added HPS JTAG timing specifications.  
Updated the configuration .rbf size (bits) for Cyclone V devices.  
Added a note to Uncompressed .rbf Sizes for Cyclone V Devices table: The recommended EPCQ serial  
configuration devices are able to store more than one image.  
July 2014  
3.9  
•
Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC  
(static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN  
tool for the additional budget for the dynamic tolerance requirements.  
Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V.  
Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20.  
Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34.  
Updated description in “HPS PLL Specifications” section.  
Updated VCO range maximum specification in Table 35.  
Updated Td and Th specifications in Table 41.  
Added Th specification in Table 43 and Figure 10.  
Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK floating after configu‐  
ration. DCLK is ignored after configuration is complete. It can toggle high or low if required.  
Removed “Remote update only in AS mode” specification in Table 54.  
Added DCLK device initialization clock source specification in Table 56.  
Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration  
via Protocol (CvP) feature.  
•
•
•
•
•
•
•
•
•
•
•
•
•
Added "Recommended EPCQ Serial Configuration Device" values in Table 57.  
Removed fMAX_RU_CLK specification in Table 59.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
1...89909192939495

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