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5CGTFD9E5F31C7N PDF预览

5CGTFD9E5F31C7N

更新时间: 2024-01-17 01:32:50
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
95页 1359K
描述
Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

5CGTFD9E5F31C7N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA896,30X30,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
JESD-30 代码:S-PBGA-B896JESD-609代码:e1
长度:31 mm湿度敏感等级:3
输入次数:448逻辑单元数量:301000
输出次数:448端子数量:896
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA896,30X30,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.1,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:31 mmBase Number Matches:1

5CGTFD9E5F31C7N 数据手册

 浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第87页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第88页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第89页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第91页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第92页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第93页 
CV-51002  
2015.12.04  
90  
Document Revision History  
Date  
Version  
Changes  
June 2015  
2015.06.12  
Updated the supported data rates for the following output standards using true LVDS output buffer types in  
the High-Speed I/O Specifications for Cyclone V Devices table:  
True RSDS output standard: data rates of up to 360 Mbps  
True mini-LVDS output standard: data rates of up to 400 Mbps  
Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.  
Updated Th location in I2C Timing Diagram.  
Updared Twp location in NAND Address Latch Timing Diagram.  
Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configu‐  
rations in Cyclone V Devices table.  
Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades  
in Cyclone V Devices chapter.  
FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1  
FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1  
AS Configuration Timing Waveform  
PS Configuration Timing Waveform  
March 2015  
2015.03.31  
Added VCC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended  
Operating Conditions table.  
Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for  
Cyclone V Devices table.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  

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