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5CGTFD9E5F31C7N PDF预览

5CGTFD9E5F31C7N

更新时间: 2024-01-23 22:07:04
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
95页 1359K
描述
Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

5CGTFD9E5F31C7N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA896,30X30,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
JESD-30 代码:S-PBGA-B896JESD-609代码:e1
长度:31 mm湿度敏感等级:3
输入次数:448逻辑单元数量:301000
输出次数:448端子数量:896
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA896,30X30,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.1,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:31 mmBase Number Matches:1

5CGTFD9E5F31C7N 数据手册

 浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第86页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第87页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第88页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第90页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第91页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第92页 
CV-51002  
2015.12.04  
89  
Document Revision History  
Term  
Definition  
VOX  
W
Output differential cross point voltage  
High-speed I/O block—Clock boost factor  
Document Revision History  
Date  
Version  
Changes  
December 2015  
2015.12.04  
Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices table.  
Updated Fclk, Tdutycycle, and Tdssfrst specifications.  
Added Tqspi_clk, Tdin_start, and Tdin_end specifications.  
Removed Tdinmax specifications.  
Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI  
Master Timing Requirements for Cyclone V Devices table.  
Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table.  
Updated T clk to Tsdmmc_clk_out symbol.  
Updated Tsdmmc_clk_out and Td specifications.  
Added Tsdmmc_clk, Tsu, and Th specifications.  
Removed Tdinmax specifications.  
Updated the following diagrams:  
Quad SPI Flash Timing Diagram  
SD/MMC Timing Diagram  
Updated configuration .rbf sizes for Cyclone V devices.  
Changed instances of Quartus II to Quartus Prime.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  

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