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5962R9957201QYC

更新时间： 2024-10-29 15:46:07
品牌 Logo 应用领域
赛灵思 - XILINX 栅可编程逻辑
页数 文件大小 规格书
17页 603K
描述
Field Programmable Gate Array, 322970 Gates, 6912-Cell, CMOS, CQFP228, QFP-228

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5962R9957201QYC 技术参数

生命周期：Active零件包装代码：QFP
包装说明：GQFF, TPAK228,2.5SQ,25针数：228
Reach Compliance Code：compliantECCN代码：9A515.E.2
HTS代码：8542.39.00.01风险等级：5.01
CLB-Max的组合延迟：0.8 nsJESD-30 代码：S-CQFP-F228
JESD-609代码：e4长度：39.37 mm
可配置逻辑块数量：1536等效关口数量：322970
输入次数：162逻辑单元数量：6912
输出次数：162端子数量：228
最高工作温度：125 °C最低工作温度：-55 °C
组织：322970 GATES封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：GQFF封装等效代码：TPAK228,2.5SQ,25
封装形状：SQUARE封装形式：FLATPACK, GUARD RING
电源：1.2/3.6,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：3.0226 mm子类别：Field Programmable Gate Arrays
最大供电电压：2.625 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：GOLD端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
总剂量：100k Rad(Si) V宽度：39.37 mm
Base Number Matches：1

5962R9957201QYC 数据手册

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17  
QPro Virtex 2.5V Radiation-Hardened FPGAs  
DS028 (v2.1) November 5, 2010  
Product Specification  
Features  
•
•
•
0.22 µm 5-layer epitaxial process  
•
Supported by FPGA Foundation™ and Alliance  
Development Systems  
QML certified  
•
Complete support for Unified Libraries, Relationally  
Placed Macros, and Design Manager  
Radiation-hardened FPGAs for space and satellite  
applications  
•
Wide selection of PC and workstation platforms  
•
•
•
Guaranteed total ionizing dose to 100K Rad(si)  
•
•
SRAM-based in-system configuration  
2
Latch-up immune to LET = 125 MeV cm /mg  
•
•
Unlimited reprogrammability  
Four programming modes  
SEU immunity achievable with recommended  
redundancy implementation  
•
•
Guaranteed over the full military temperature range  
(–55°C to +125°C)  
Available to Standard Microcircuit Drawings. Contact  
Defense Supply Center Columbus (DSCC) for more  
information at http://www.dscc.dla.mil  
Fast, high-density Field-Programmable Gate Arrays  
•
•
•
5962-99572 for XQVR300  
5962-99573 for XQVR600  
5962-99574 for XQVR1000  
•
•
•
Densities from 100k to 1M system gates  
System performance up to 200 MHz  
Hot-swappable for Compact PCI  
•
•
Multi-standard SelectIO™ interfaces  
Description  
•
•
16 high-performance interface standards  
Connects directly to ZBTRAM devices  
The QPro™ Virtex® family delivers high-performance,  
high-capacity programmable logic solutions. Dramatic  
increases in silicon efficiency result from optimizing the new  
architecture for place-and-route efficiency and exploiting an  
aggressive 5-layer-metal 0.22 µm CMOS process. These  
advances make QPro Virtex FPGAs powerful and flexible  
alternatives to mask-programmed gate arrays. The Virtex  
radiation-hardened family comprises the three members  
shown in Table 1.  
Built-in clock-management circuitry  
•
Four dedicated delay-locked loops (DLLs) for  
advanced clock control  
•
Four primary low-skew global clock distribution  
nets, plus 24 secondary global nets  
•
•
Hierarchical memory system  
•
•
•
LUTs configurable as 16-bit RAM, 32-bit RAM,  
16-bit dual-ported RAM, or 16-bit Shift Register  
Building on experience gained from previous generations of  
FPGAs, the Virtex family represents a revolutionary step  
forward in programmable logic design. Combining a wide  
variety of programmable system features, a rich hierarchy of  
fast, flexible interconnect resources, and advanced process  
technology, the QPro Virtex family delivers a high-speed  
and high-capacity programmable logic solution that  
Configurable synchronous dual-ported 4k-bit  
RAMs  
Fast interfaces to external high-performance RAMs  
Flexible architecture that balances speed and density  
•
•
•
•
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
enhances design flexibility while reducing time-to-market.  
Refer to the Virtex 2.5V FPGA commercial data sheet at  
http://www.xilinx.com/support/documentation/virtex.htm for  
more information on device architecture and timing  
specifications.  
Cascade chain for wide-input functions  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
•
•
•
Internal 3-state bussing  
IEEE 1149.1 boundary-scan logic  
Die-temperature sensing device  
© Copyright 2001–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. All other trademarks are the property of their respective owners.  
DS028 (v2.1) November 5, 2010  
www.xilinx.com  
Product Specification  
1
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