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5962R9672502TRX

更新时间： 2024-10-28 21:17:43
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动输出元件逻辑集成电路
页数 文件大小 规格书
3页 40K
描述
ACT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, CDIP20, SIDE BRAZED, CERAMIC, DIP-20

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5962R9672502TRX 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61系列：ACT
JESD-30 代码：R-CDIP-T20逻辑集成电路类型：BUS DRIVER
位数：1功能数量：8
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：18 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class T座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL总剂量：100k Rad(Si) V
宽度：7.62 mmBase Number Matches：1

5962R9672502TRX 数据手册

 浏览型号5962R9672502TRX的Datasheet PDF文件第2页浏览型号5962R9672502TRX的Datasheet PDF文件第3页 
ACTS573T  
Data Sheet  
July 1999  
File Number 4613.1  
Radiation Hardened Octal Three-State  
Transparent Latch  
Features  
• QML Class T, Per MIL-PRF-38535  
Intersil’s Satellite Applications FlowTM (SAF) devices are fully  
tested and guaranteed to 100kRAD total dose. These QML  
Class T devices are processed to a standard flow intended  
to meet the cost and shorter lead-time needs of large  
volume satellite manufacturers, while maintaining a high  
level of reliability.  
• Radiation Performance  
5
- Gamma Dose (γ) 1 x 10 RAD(Si)  
- Latch-Up Free Under Any Conditions  
-10  
- Single Event Upset (SEU) Immunity: <1 x 10  
Errors/Bit/Day (Typ)  
2
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm /mg  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range. . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
The Intersil ACTS573T is a Radiation Hardened Octal  
Transparent Latch with an active low output enable. The  
outputs are transparent to the inputs when the latch enable  
(LE) is High. When the latch goes low the data is latched.  
The output enable controls the three-state outputs. When  
the output enable pins (OE) are high the output is in a high  
impedance state. The latch operation is independent of the  
state of output enable.  
- V = 0.8V Max  
IL  
- V = VCC/2 Min  
IH  
• Fast Propagation Delay . . . . . . . . 18ns (Max), 12ns (Typ)  
Specifications  
Specifications for Rad Hard QML devices are controlled by  
the Defense Supply Center in Columbus (DSCC). The SMD  
numbers listed below must be used when ordering.  
Pinouts  
ACTS573T (SBDIP), CDIP2-T20  
TOP VIEW  
Detailed Electrical Specifications for the ACTS573T are  
contained in SMD 5962-96725. A “hot-link” is provided from  
our website for downloading.  
1
2
3
4
5
6
7
8
9
V
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
CC  
Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
www.intersil.com/spacedefense/newsafclasst.asp  
Intersil’s Quality Management Plan (QM Plan), listing all  
Class T screening operations, is also available on our  
website.  
www.intersil.com/quality/manuals.asp  
12  
Q7  
Ordering Information  
GND 10  
11 LE  
TEMP.  
ORDERING  
INFORMATION  
PART  
NUMBER  
RANGE  
( C)  
o
ACTS573T (FLATPACK), CDFP4-F20  
5962R9672502TRC  
5962R9672502TXC  
ACTS573DTR-02  
ACTS573KTR-02  
-55 to 125  
-55 to 125  
TOP VIEW  
OE  
D0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
NOTE: Minimum order quantity for -T is 150 units through  
distribution, or 450 units direct.  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q7  
LE  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
123

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