生命周期: | Obsolete | 零件包装代码: | DFP |
包装说明: | DFP, | 针数: | 14 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.84 | Is Samacsys: | N |
JESD-609代码: | e4 | 长度: | 9.525 mm |
逻辑集成电路类型: | NAND GATE | 功能数量: | 1 |
输入次数: | 8 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | CERAMIC, METAL-SEALED COFIRED |
封装代码: | DFP | 封装形式: | FLATPACK |
传播延迟(tpd): | 16 ns | 认证状态: | Not Qualified |
座面最大高度: | 2.92 mm | 表面贴装: | YES |
技术: | CMOS | 温度等级: | MILITARY |
端子面层: | GOLD | 端子形式: | FLAT |
端子节距: | 1.27 mm | 端子位置: | DUAL |
总剂量: | 300k Rad(Si) V | 宽度: | 6.285 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
5962F9863101VXX | WEDC |
获取价格 |
IC 8-INPUT NAND GATE, CDFP, CERAMIC, DFP-14, Gate |
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5962F9863201V9A | INTERSIL |
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Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
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5962F9863201V9A | RENESAS |
获取价格 |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16 |
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5962F9863201VCC | INTERSIL |
获取价格 |
Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
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5962F9863201VCC | RENESAS |
获取价格 |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE |
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5962F9863201VEC | ETC |
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J-K-Type Flip-Flop |
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5962F9863201VEX | WEDC |
获取价格 |
J-K Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CM |
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5962F9863201VXC | INTERSIL |
获取价格 |
Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
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5962F9863201VXX | WEDC |
获取价格 |
IC AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CE |
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5962F9863301V9A | INTERSIL |
获取价格 |
Radiation Hardened 10-to-4 Line Priority Encoder |
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