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5962-JM38510/55501BZC PDF预览

5962-JM38510/55501BZC

更新时间： 2022-11-24 21:17:35
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
52页 1271K
描述
RTI Remote Terminal Interface

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5962-JM38510/55501BZC 数据手册

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The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero  
to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control  
Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in  
the outgoing status word.  
Bit  
Initial  
Number  
Condition  
Description  
0
1
2
3
[0]  
[0]  
[0]  
[0]  
Channel A Enable. A logic one enables Channel A biphase inputs.  
Channel B Enable. A logic one enables Channel B biphase inputs.  
Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register.  
System Busy. A logic one sets the Busy bit of the System Register and inhibits  
RTI access to memory. No data words are retrieved or stored; command word is  
stored.  
4
5
[0]  
[0]  
Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register.  
Self-Test Channel Select. This bit selects which channel the internal self-test  
checks; a logic one selects Channel A and a logic zero selects Channel B.  
6
[0]  
Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhib-  
its normal operation. Internal testing is not visible on biphase output  
channels.  
7
[0]  
Service Request. A logic one sets the Service Request bit of the Status Register.  
CONTROL REGISTER (WRITE ONLY)  
TF  
[0]  
CH B  
EN  
BUSY  
[0]  
CH A  
EN  
SUBS  
[0]  
SELF  
TEST  
SELF  
CH  
SRV  
RQ  
X
X
X
X
X
X
X
X
[0]  
[0]  
[0]  
[0]  
[0]  
LSB  
MSB  
[ ] defines reset state  
Figure 4. Control Register  
System Register (Read Only)  
The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to  
CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins  
DATA(15:0).  
Bit  
Initial  
Number  
Condition  
Description  
0
[0]  
MCSA(0). The LSB of the mode code or subaddress as indicated by the  
logic state of bit 5.  
1
2
3
4
5
[0]  
[0]  
[0]  
[0]  
[0]  
MCSA(1). Mode code or subaddress as indicated by the state of bit 5.  
MCSA(2). Mode code or subaddress as indicated by the state of bit 5.  
MCSA(3). Mode code or subaddress as indicated by the state of bit 5.  
MCSA(4). Mode code or subaddress as indicated by the state of bit 5.  
MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of  
the last command word, and that the last command word was a normal  
transmit orreceive command. A logic zero indicates that bits 4 through 0  
are a mode code, and that the last command was a mode code.  
6
[1]  
Channel A/B. A logic one indicates that the most recent command arrived  
onChannel A; a logic zero indicates that it arrived on Channel B.  
RTI-5  
12345678...52

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