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5962-9956501HTC PDF预览

5962-9956501HTC

更新时间: 2024-10-28 20:29:03
品牌 Logo 应用领域
CRANE 局域网输出元件
页数 文件大小 规格书
16页 465K
描述
Analog Circuit, Hybrid,

5962-9956501HTC 技术参数

生命周期:Contact Manufacturer包装说明:, MODULE,12LEAD,2.5
Reach Compliance Code:compliantECCN代码:EAR99
风险等级:5.53其他特性:ADDITIONAL -6.3V OUTPUT AVAILABLE
模拟集成电路 - 其他类型:DC-DC REGULATED POWER SUPPLY MODULE最大输入电压:40 V
最小输入电压:16 V标称输入电压:28 V
JESD-30 代码:R-MUFM-P12JESD-609代码:e4
功能数量:1输出次数:2
端子数量:12最高工作温度:125 °C
最低工作温度:-55 °C最大输出电流:16 A
最大输出电压:6.36 V最小输出电压:6.24 V
标称输出电压:6.3 V封装主体材料:METAL
封装等效代码:MODULE,12LEAD,2.5封装形状:RECTANGULAR
封装形式:FLANGE MOUNT认证状态:Qualified
筛选级别:MIL-PRF-38534子类别:Other Analog ICs
表面贴装:NO技术:HYBRID
温度等级:MILITARY端子面层:GOLD
端子形式:PIN/PEG端子位置:UPPER
最大总功率输出:100 W微调/可调输出:YES
Base Number Matches:1

5962-9956501HTC 数据手册

 浏览型号5962-9956501HTC的Datasheet PDF文件第2页浏览型号5962-9956501HTC的Datasheet PDF文件第3页浏览型号5962-9956501HTC的Datasheet PDF文件第4页浏览型号5962-9956501HTC的Datasheet PDF文件第6页浏览型号5962-9956501HTC的Datasheet PDF文件第7页浏览型号5962-9956501HTC的Datasheet PDF文件第8页 
MOR SERIES  
120 WATT  
DC/DC CONVERTERS  
PIN DESCRIPTIONS AND FUNCTIONS  
TRIM  
Trim  
3
RT  
7
10  
TRIM UP  
Both single and dual output  
models include a trim function.  
Output voltage can be trimmed  
from 60% up to 110% of nominal  
V out . When trimming up, do not  
exceed the maximum output  
power. When trimming down, do  
not exceed the maximum output  
current.  
Positive Output  
Positive Sense  
MOR  
Single  
Output  
PIN OUT  
9
8
Sense Return  
Pin  
Single Output  
Dual Output  
Output Common  
TRIM  
DOWN  
1
2
Positive Input  
Input Common  
Trim  
Positive Input  
Input Common  
Case  
FIGURE 3:TRIM – SINGLE  
Trim  
RT  
10  
3
TRIM UP  
7
8
Positive Output  
4
Inhibit 1(INH1)  
Sync Out  
Inhibit 1(INH1)  
Sync Out  
MOR  
Dual  
Output  
Output Common  
5
Trim Formulas  
TRIM DOWN  
6
Sync In  
Sync In  
9
Negative Output  
V
o
Trim Up: α =  
V
o nominal  
, 1.0 ≤ α ≤ 1.1  
7
Positive Output  
Positive Output  
V
2.5  
o
FIGURE 4:TRIM – DUAL  
8
Output Common Output Common  
(
(k) =  
1  
)
20  
R
50  
T
(α -1)  
9
Sense Return  
Positive Sense  
Share  
Negative Output  
Trim  
On dual models the positive  
output is regulated and the  
negative output is transformer  
coupled (cross-regulated) to the  
positive output. When trimming  
the duals, both output voltages  
will be adjusted equally.  
Example:  
V
= 5.0,  
V
o
= 5.25,  
o nominal  
10  
11  
12  
α = 1.05,  
R
= 390 kΩ  
T
Share  
V
o
Trim Down: α =  
, 0.6 ≤ α ≤ 1.0  
V
o nominal  
Inhibit 2 (INH2)  
Inhibit 2 (INH2)  
50 α 30  
1 α  
R
(k) =  
T
Example:  
V
= 5.0, V = 4.5,  
o nominal o  
POSITIVE INPUT AND INPUT COMMON  
α = 0.9,  
R = 150 kΩ  
T
Steady state voltage range is 16 to 40 VDC. Transient range is 40  
to 50 V for a maximum of 120 msec. Low voltage lockout prevents  
the units from operating below approximately 15.5 VDC input  
voltage to keep system current levels smooth, especially during  
initialization or re-start operations. All models include a soft-start  
function to prevent large current draw and minimize overshoot.  
INHIBIT 1 AND 2  
Two inhibit terminals disable switching, resulting in no output and  
very low quiescent input current. The two inhibit pins allow access  
to an inhibit function on either side of the isolation barrier to help  
maintain isolation.  
CASE AND EXTERNAL INPUT FILTERS  
Internal 500 V capacitors are connected between the case and  
input common and between the case and output common. See  
Figure 1.  
Positive  
An open collector is  
Input  
required for inter-  
facing with both of  
the inhibit pins.  
Applying an open-  
collector TTL logic  
low to either inhibit  
pin will inhibit the  
converter. Applying  
an open collector  
TTL logic high or  
leaving the pins  
200  
20 k  
12 V  
Interpoint’s FME filters are recommended to meet CE03 require-  
ments for reflected input line current. When using an external  
input filter it is important that the case of the filter and the case of  
the converter be connected through as low as an impedance as  
possible. Direct connection of the baseplates to chassis ground is  
the best connection. If connected by a single trace, the trace  
should be as wide as it is long.  
10 k  
Inhibit 1  
VCC  
Input  
Common  
MOR Input Side  
FIGURE 5: INHIBIT – INPUT SIDE  
open will enable the converter. Inhibit 1 is referenced to Input  
Common, while Inhibit 2 is referenced to Sense Return on the  
output side.  
1, 2, 3  
10, 11, 12  
1
2
Positive Input  
Positive Output  
Positive Input  
MOR  
Single or Dual  
Output  
VS  
FME28-461  
EMI Filter  
The  
open  
circuit  
~
~
28V  
Voltage  
E/A  
Current  
Limit  
voltage for Inhibit 1 is  
13 V and for Inhibit 2 it  
is 8 V. Float the inhibit  
pin(s) if not used. The  
required logic low  
voltage level is 0.2  
maximum.  
10 k  
4, 5, 6  
Input Common  
7, 8, 9  
Case*  
Input Common  
Output Common  
200 Ω  
Feedback  
Inhibit 2  
Chassis Ground  
V
FIGURE 2: EXTERNAL FILTER CONNECTION  
Sense  
Return  
MOR Output Side  
FIGURE 6: INHIBIT – OUTPUT SIDE  
5

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