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5962-9851101QYC

更新时间: 2024-11-13 20:32:31
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
22页 170K
描述
Field Programmable Gate Array, 2304 CLBs, 40000 Gates, 166MHz, 5472-Cell, CMOS, CQFP228, CERAMIC, QFP-228

5962-9851101QYC 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:GQFF, TPAK228,2.5SQ,25针数:228
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:MAXIMUM USABLE GATES 130000
最大时钟频率:166 MHzCLB-Max的组合延迟:1.6 ns
JESD-30 代码:S-CQFP-F228JESD-609代码:e4
长度:39.37 mm可配置逻辑块数量:2304
等效关口数量:40000输入次数:192
逻辑单元数量:5472输出次数:192
端子数量:228最高工作温度:125 °C
最低工作温度:-55 °C组织:2304 CLBS, 40000 GATES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:GQFF
封装等效代码:TPAK228,2.5SQ,25封装形状:SQUARE
封装形式:FLATPACK, GUARD RING电源:3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class Q座面最大高度:3.302 mm
子类别:Field Programmable Gate Arrays最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:GOLD
端子形式:FLAT端子节距:0.635 mm
端子位置:QUAD宽度:39.37 mm
Base Number Matches:1

5962-9851101QYC 数据手册

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R
QPRO XQ4000XL Series QML  
High-Reliability FPGAs  
0
2
DS029 (v1.3) June 25, 2000  
Product Specification  
Development system runs on most common computer  
platforms  
XQ4000X Series Features  
Certified to MIL-PRF-38535 Appendix A QML  
(Qualified Manufacturer Listing)  
-
-
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Interfaces to popular design environments  
Fully automatic mapping, placement and routing  
Interactive design editor for design optimization  
Ceramic and plastic packages  
Also available under the following standard microcircuit  
drawings (SMD)  
Highest capacityover 180,000 usable gates  
Additional routing over XQ4000E  
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-
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XQ4013XL 5962-98513  
XQ4036XL 5962-98510  
XQ4062XL 5962-98511  
XQ4085XL 5962-99575  
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Almost twice the routing capacity for high-density  
designs  
Buffered Interconnect for maximum speed  
New latch capability in configurable logic blocks  
For more information contact the Defense Supply  
Center Columbus (DSCC)  
Improved VersaRingI/O interconnect for better Fixed  
pinout flexibility  
http://www.dscc.dla.mis/v/va/smd/smdsrch.html  
-
Virtually unlimited number of clock signals  
Available in -3 speed  
Optional multiplexer or 2-input function generator on  
device outputs  
System featured Field-Programmable Gate Arrays  
-
SelectRAM™ memory: on-chip ultra-fast RAM with  
5V tolerant I/Os  
·
·
synchronous write option  
dual-port RAM option  
0.35 µm SRAM process  
-
-
-
-
-
-
-
Abundant flip-flops  
Introduction  
Flexible function generators  
Dedicated high-speed carry logic  
Wide edge decoders on each edge  
Hierarchy of interconnect lines  
Internal 3-state bus capability  
Eight global low-skew clock or signal distribution  
networks  
The QPROXQ4000XL Series high-performance,  
high-capacity Field Programmable Gate Arrays (FPGAs)  
provide the benefits of custom CMOS VLSI, while avoiding  
the initial cost, long development cycle, and inherent risk of  
a conventional masked gate array.  
The result of thirteen years of FPGA design experience and  
feedback from thousands of customers, these FPGAs com-  
bine architectural versatility, on-chip Select-RAM memory  
with edge-triggered and dual-port modes, increased speed,  
abundant routing resources, and new, sophisticated  
soft-ware to achieve fully automated implementation of  
complex, high-density, high-performance designs.  
System performance beyond 50 MHz  
Flexible array architecture  
Low power segmented routing architecture  
Systems-oriented features  
-
IEEE 1149.1-compatible boundary scan logic  
support  
Refer to the complete Commercial XC4000XL Series Field  
Programmable Gate Arrays Data Sheet for more informa-  
tion on device architecture and timing, and the latest Xilinx  
databook for package pinouts other than the CB228  
(included in this data sheet). (Pinouts for XQ4000XL device  
are identical to XC4000XL.)  
-
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Individually programmable output slew rate  
Programmable input pull-up or pull-down resistors  
12 mA sink current per XQ4000XL output  
Configured by loading binary file  
Unlimited reprogrammability  
Readback capability  
-
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Program verification  
Internal node observability  
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS029 (v1.3) June 25, 2000  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  

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